iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-5/+5
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-99/+99
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-99/+99
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-60/+16
*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23	1	-98/+45
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-56/+56
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-56/+56
*	Removed deprecated module->new_wire()	Clifford Wolf	2014-07-21	1	-4/+4
*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07	1	-0/+18
*	Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen)	Clifford Wolf	2013-12-29	1	-2/+2
*	Added new cell types to manual	Clifford Wolf	2013-12-28	1	-1/+1
*	Added $bu0 cell (for easy correct $eq/$ne mapping)	Clifford Wolf	2013-12-28	1	-0/+13
*	Using simplemap mappers from techmap	Clifford Wolf	2013-11-24	1	-25/+30
*	Added simplemap pass	Clifford Wolf	2013-11-24	1	-0/+517