iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-1/+1
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*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-7/+2
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-4/+4
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-4/+4
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at\("([^"])"\)/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-4/+4
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*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-8/+2
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*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-2/+2
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*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	1	-2/+2
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*	Added support for "blackbox" attribute to iopadmap	Clifford Wolf	2014-07-17	1	-1/+1
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*	Added iopadmap -bits	Clifford Wolf	2014-02-15	1	-14/+48
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*	Added support for i/o buffers to iopadmap	Clifford Wolf	2013-10-26	1	-10/+35
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*	Fixed handling of boolean attributes (passes)	Clifford Wolf	2013-10-24	1	-1/+1
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*	Added iopadmap pass	Clifford Wolf	2013-10-16	1	-0/+159