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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 14:32:50 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 15:58:23 +0200 |
| commit | b7dda723022ad00c6c0089be888eab319953faa8 (patch) | |
| tree | 4fe12ce120f1809891dc4cbd862bbcdab0e90fcc /passes/techmap/iopadmap.cc | |
| parent | cd6574ecf652901573cbc6b89e1a59dd383ec496 (diff) | |
| download | yosys-b7dda723022ad00c6c0089be888eab319953faa8.tar.gz yosys-b7dda723022ad00c6c0089be888eab319953faa8.tar.bz2 yosys-b7dda723022ad00c6c0089be888eab319953faa8.zip | |
Changed users of cell->connections_ to the new API (sed command)
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
Diffstat (limited to 'passes/techmap/iopadmap.cc')
| -rw-r--r-- | passes/techmap/iopadmap.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index ba9bf51d3..199fd6029 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -177,9 +177,9 @@ struct IopadmapPass : public Pass { for (int i = 0; i < wire->width; i++) { RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype)); - cell->connections_[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, i); + cell->connections()[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, i); if (!portname2.empty()) - cell->connections_[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, i); + cell->connections()[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, i); if (!widthparam.empty()) cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1); if (!nameparam.empty()) @@ -190,9 +190,9 @@ struct IopadmapPass : public Pass { else { RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype)); - cell->connections_[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire); + cell->connections()[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire); if (!portname2.empty()) - cell->connections_[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire); + cell->connections()[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire); if (!widthparam.empty()) cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width); if (!nameparam.empty()) |