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* Remove &verify -sEddie Hung2019-12-171-1/+1
* Use pool<> instead of std::set<> to preserver orderingEddie Hung2019-12-171-6/+6
* Put $__ABC9_{FF_,ASYNC} into same clock domain as abc9_flopEddie Hung2019-12-161-5/+27
* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-061-29/+40
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| * abc9: Fix breaking of SCCsDavid Shah2019-12-011-29/+40
| * Merge branch 'master' into eddie/abc_to_abc9Eddie Hung2019-10-041-3/+12
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* | | Call abc9 with "&write -n", and parse_xaiger() to copeEddie Hung2019-12-061-2/+2
* | | Fix abc9 re-integration, remove abc9_control_wire, use cell->type asEddie Hung2019-12-061-39/+15
* | | abc9 to do clock partitioning againEddie Hung2019-12-051-37/+144
* | | Add assertionEddie Hung2019-12-031-0/+1
* | | Add abc9_init wire, attach to abc9_flop cellEddie Hung2019-12-031-2/+12
* | | CleanupEddie Hung2019-12-011-3/+2
* | | Fix debugEddie Hung2019-11-251-3/+3
* | | abc9 to contain time callEddie Hung2019-11-251-1/+1
* | | abc9 to no longer to clock partitioning, operate on whole modules onlyEddie Hung2019-11-251-139/+32
* | | Conditioning abc9 on POs not accurate due to cellsEddie Hung2019-11-231-15/+6
* | | When expanding upwards, do not capture $__ABC9_{FF,ASYNC}_Eddie Hung2019-11-211-1/+1
* | | endomain -> ctrldomainEddie Hung2019-11-201-3/+3
* | | Use "abc9_period" attribute for delay targetEddie Hung2019-10-071-3/+24
* | | Do not require changes to cells_sim.v; try and work out comb modelEddie Hung2019-10-051-30/+6
* | | Fix from mergeEddie Hung2019-10-041-1/+1
* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-041-2/+12
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| * | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`Eddie Hung2019-10-041-3/+13
* | | Fix merge issuesEddie Hung2019-10-041-2/+2
* | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dffEddie Hung2019-10-041-68/+67
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| * | Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-041-65/+65
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* | No need to punch ports at allEddie Hung2019-09-301-13/+0
* | Resolve FIXME on calling proc just onceEddie Hung2019-09-301-2/+2
* | Add commentEddie Hung2019-09-301-0/+1
* | scc call on active module module only, plus cleanupEddie Hung2019-09-301-21/+16
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-301-1/+1
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| * Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_inMiodrag Milanović2019-09-301-1/+1
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| | * Open aig frontend as binary fileMiodrag Milanovic2019-09-291-1/+1
* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-291-3/+16
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| * | "abc_padding" attr for blackbox outputs that were padded, remove them laterEddie Hung2019-09-231-3/+16
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* | Fix "scc" call inside abc9 to consider all wiresEddie Hung2019-09-291-1/+1
* | Big rework; flop info now mostly in cells_sim.vEddie Hung2019-09-281-78/+65
* | Split ABC9 based on clocking only, add "abc_mergeability" attr for enEddie Hung2019-09-271-88/+28
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-271-109/+43
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| * Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-301-16/+10
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| | * Output has priority over input when stitching in abc9Eddie Hung2019-08-291-13/+10
| | * abc9 to not call "clean" at end of run (often called outside)Eddie Hung2019-08-291-3/+0
| * | Use a dummy box file if none specifiedEddie Hung2019-08-281-3/+8
| * | CleanupEddie Hung2019-08-231-130/+59
* | | Revert "Remove sequential extension"Eddie Hung2019-08-201-20/+68
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* | Remove sequential extensionEddie Hung2019-08-201-68/+20
* | retime_mode -> dff_modeEddie Hung2019-08-201-7/+7
* | Fix use of {CLK,EN}_POLARITY, also add a FIXMEEddie Hung2019-08-201-65/+13
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-08-201-6/+6
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| * Merge pull request #1304 from YosysHQ/eddie/abc9_refactorEddie Hung2019-08-201-43/+80
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