| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | rtlil: Make Process handling more uniform with Cell and Wire. | Marcelina Kościelnicka | 2021-07-12 | 1 | -5/+4 |
| | | | | | | | - add a backlink to module from Process - make constructor and destructor protected, expose Module functions to add and remove processes | ||||
| * | Fixing old e-mail addresses and deadnames | Claire Xenia Wolf | 2021-06-08 | 1 | -1/+1 |
| | | | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g; | ||||
| * | Add support for memory writes in processes. | Marcelina Kościelnicka | 2021-03-08 | 1 | -1/+1 |
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| * | proc_clean: Fix empty case removal conditions. | Marcelina Kościelnicka | 2021-03-06 | 1 | -10/+21 |
| | | | | | Fixes #2639. | ||||
| * | Use C++11 final/override keywords. | whitequark | 2020-06-18 | 1 | -2/+2 |
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| * | proc_clean: fix order of switch insertion. | whitequark | 2019-08-19 | 1 | -2/+1 |
| | | | | | Fixes #1268. | ||||
| * | proc_clean: add -quiet option. | whitequark | 2019-07-09 | 1 | -8/+24 |
| | | | | | This is useful for other passes that call it often, like bugpoint. | ||||
| * | proc_clean: fix critical typo. | whitequark | 2019-01-23 | 1 | -1/+1 |
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| * | proc_clean: fix fully def check to consider compare/signal length. | whitequark | 2019-01-18 | 1 | -1/+7 |
| | | | | | Fixes #790. | ||||
| * | proc_clean: remove any empty cases if all cases use all-def compare. | whitequark | 2018-12-23 | 1 | -6/+28 |
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| * | proc_clean: remove any empty cases at the end of the switch. | whitequark | 2018-12-22 | 1 | -7/+3 |
| | | | | | Previously, only completely empty switches were removed. | ||||
| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -2/+2 |
| | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) | ||||
| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 |
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| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -3/+3 |
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| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -2/+13 |
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| * | Fixed handling of constant-true branches in proc_clean | Clifford Wolf | 2014-08-12 | 1 | -1/+2 |
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| * | More cleanups related to RTLIL::IdString usage | Clifford Wolf | 2014-08-02 | 1 | -1/+1 |
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| * | Using new obj iterator API in a few places | Clifford Wolf | 2014-07-27 | 1 | -8/+8 |
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| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
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| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -4/+4 |
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| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -4/+4 |
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| * | Added handling of multiple async paths in proc_arst | Clifford Wolf | 2013-10-19 | 1 | -8/+9 |
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| * | Added help messages to proc_* passes | Clifford Wolf | 2013-03-01 | 1 | -1/+15 |
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| * | initial import | Clifford Wolf | 2013-01-05 | 1 | -0/+160 |
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index : iCE40/yosys | |
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