| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Fixing old e-mail addresses and deadnames | Claire Xenia Wolf | 2021-06-08 | 1 | -1/+1 |
| * | proc_arst: Add special-casing of clock signal in conditionals. | Marcelina Kościelnicka | 2021-03-15 | 1 | -23/+51 |
| * | Add support for memory writes in processes. | Marcelina Kościelnicka | 2021-03-08 | 1 | -20/+34 |
| * | Use C++11 final/override keywords. | whitequark | 2020-06-18 | 1 | -2/+2 |
| * | kernel: big fat patch to use more ID::*, otherwise ID(*) | Eddie Hung | 2020-04-02 | 1 | -9/+9 |
| * | kernel: use more ID::* | Eddie Hung | 2020-04-02 | 1 | -22/+22 |
| * | Make liberal use of IdString.in() | Eddie Hung | 2019-08-06 | 1 | -2/+2 |
| * | proc_prune: promote assigns to module connections when legal. | whitequark | 2019-07-09 | 1 | -1/+1 |
| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -2/+2 |
| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 |
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -3/+3 |
| * | Minor fixes in handling of "init" attribute | Clifford Wolf | 2015-04-09 | 1 | -0/+5 |
| * | Removed SigSpec::extend_xx() api | Clifford Wolf | 2015-01-01 | 1 | -1/+1 |
| * | Renamed extend() to extend_xx(), changed most users to extend_u0() | Clifford Wolf | 2014-12-24 | 1 | -1/+1 |
| * | Renamed SIZE() to GetSize() because of name collision on Win32 | Clifford Wolf | 2014-10-10 | 1 | -1/+1 |
| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -5/+10 |
| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -22/+22 |
| * | Using new obj iterator API in a few places | Clifford Wolf | 2014-07-27 | 1 | -10/+15 |
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -2/+2 |
| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -22/+22 |
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -22/+22 |
| * | Fixed all users of SigSpec::chunks_rw() and removed it | Clifford Wolf | 2014-07-23 | 1 | -5/+3 |
| * | SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created... | Clifford Wolf | 2014-07-22 | 1 | -1/+1 |
| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -9/+9 |
| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -9/+9 |
| * | Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst | Clifford Wolf | 2014-02-21 | 1 | -2/+6 |
| * | Added support for non-const === and !== (for miter circuits) | Clifford Wolf | 2013-12-27 | 1 | -2/+2 |
| * | Added "proc_arst -global_arst" feature | Clifford Wolf | 2013-11-20 | 1 | -5/+59 |
| * | Added handling of multiple async paths in proc_arst | Clifford Wolf | 2013-10-19 | 1 | -0/+12 |
| * | Added nosync attribute and some async reset related fixes | Clifford Wolf | 2013-03-25 | 1 | -0/+5 |
| * | Added help messages to proc_* passes | Clifford Wolf | 2013-03-01 | 1 | -6/+19 |
| * | initial import | Clifford Wolf | 2013-01-05 | 1 | -0/+191 |
