iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	pmgen to also iterate over all module ports	Eddie Hung	2019-08-22	1	-2/+4
*	Remove output_bits	Eddie Hung	2019-08-22	2	-16/+7
*	Forgot to set ud_variable.minlen	Eddie Hung	2019-08-22	1	-0/+1
*	Do not run xilinx_srl_pm in fixed loop	Eddie Hung	2019-08-22	1	-28/+24
*	Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl	Eddie Hung	2019-08-22	1	-1/+1
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\| *	Fix test_pmgen deps	Miodrag Milanovic	2019-08-21	1	-1/+1
* \|	Reuse var	Eddie Hung	2019-08-21	1	-1/+1
* \|	Revert "Trim shiftx_width when upper bits are 1'bx"	Eddie Hung	2019-08-21	1	-6/+1
* \|	Trim shiftx_width when upper bits are 1'bx	Eddie Hung	2019-08-21	1	-1/+6
* \|	Add comment	Eddie Hung	2019-08-21	1	-0/+4
* \|	Add variable length support to xilinx_srl	Eddie Hung	2019-08-21	2	-14/+164
* \|	Rename pattern to fixed	Eddie Hung	2019-08-21	2	-10/+10
* \|	attribute -> attr	Eddie Hung	2019-08-21	1	-4/+4
* \|	Use Cell::has_keep_attribute()	Eddie Hung	2019-08-21	1	-4/+4
* \|	xilinx_srl to support FDRE and FDRE_1	Eddie Hung	2019-08-21	2	-10/+73
* \|	Fix polarity of EN_POL	Eddie Hung	2019-08-21	1	-2/+2
* \|	Add CLKPOL == 0	Eddie Hung	2019-08-21	1	-0/+2
* \|	Reject if not minlen from inside pattern matcher	Eddie Hung	2019-08-21	2	-8/+11
* \|	Get wire via SigBit	Eddie Hung	2019-08-21	1	-4/+4
* \|	Respect \keep on cells or wires	Eddie Hung	2019-08-21	1	-2/+10
* \|	Add init support	Eddie Hung	2019-08-21	1	-2/+11
* \|	Fix spacing	Eddie Hung	2019-08-21	1	-2/+2
* \|	Initial progress on xilinx_srl	Eddie Hung	2019-08-21	3	-0/+213
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*	Fix copy-paste typo	Eddie Hung	2019-08-20	1	-1/+1
*	Merge branch 'master' into clifford/pmgen	Clifford Wolf	2019-08-20	1	-3/+1
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\| *	Ignore all generated headers for pmgen pass	Miodrag Milanovic	2019-08-18	1	-2/+1
* \|	Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen	Clifford Wolf	2019-08-19	3	-2/+109
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\| *	Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_ad...	Eddie Hung	2019-08-12	3	-0/+111
* \|	Refactor pmgen rollback mechanism	Clifford Wolf	2019-08-17	1	-32/+21
* \|	Improvements in "test_pmgen -generate"	Clifford Wolf	2019-08-17	1	-3/+23
* \|	Add pmgen "fallthrough" statement	Clifford Wolf	2019-08-17	2	-3/+17
* \|	Add help() call	Eddie Hung	2019-08-16	1	-0/+1
* \|	Minor bugfix in "test_pmgen -generate"	Clifford Wolf	2019-08-16	1	-1/+1
* \|	Add pmgen finish statement, return number of matches	Clifford Wolf	2019-08-16	4	-82/+116
* \|	Redesign pmgen backtracking for recursive matching	Clifford Wolf	2019-08-16	2	-33/+38
* \|	Add pmgen "generate" feature	Clifford Wolf	2019-08-16	3	-13/+208
* \|	Refactor demo_reduce into test_pmgen	Clifford Wolf	2019-08-16	4	-14/+83
* \|	Add doc for pmgen semioptional statement, Add pmgen changes to CHANGELOG	Clifford Wolf	2019-08-15	1	-0/+3
* \|	Update pmgen documentation	Clifford Wolf	2019-08-15	1	-4/+58
* \|	Change pmgen default rule to reject, switch peepopt behavior to accept	Clifford Wolf	2019-08-15	5	-7/+5
* \|	Add demo_reduce pass to demonstrace recursive pattern matching	Clifford Wolf	2019-08-15	4	-0/+187
* \|	Improvements in pmgen for recursive patterns	Clifford Wolf	2019-08-15	4	-26/+132
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*	Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"	David Shah	2019-08-10	3	-111/+0
*	Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER	Eddie Hung	2019-08-07	3	-0/+111
*	Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047	Clifford Wolf	2019-05-28	1	-4/+11
*	Bugfix in peepopt_shiftmul.pmg	Clifford Wolf	2019-05-06	1	-0/+4
*	Update pmgen documentation	Clifford Wolf	2019-05-03	1	-6/+18
*	Fix typo	Clifford Wolf	2019-05-03	1	-1/+1
*	Add peepopt_muldiv, fixes #930	Clifford Wolf	2019-04-30	4	-1/+41
*	pmgen progress	Clifford Wolf	2019-04-30	4	-13/+27