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passes
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pmgen
Commit message (
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Author
Age
Files
Lines
*
Create new $__XILINX_SHREG_ cell for variable length too
Eddie Hung
2019-08-23
1
-31
/
+30
*
Do not allow Q of last cell of variable length SRL to be (* keep *)
Eddie Hung
2019-08-23
1
-0
/
+1
*
Also add first.Q to chain_bits since variable length
Eddie Hung
2019-08-23
1
-0
/
+1
*
Do not enforce !EN_POLARITY on $dffe
Eddie Hung
2019-08-23
1
-2
/
+0
*
Create new cell for fixed length SRL
Eddie Hung
2019-08-23
1
-14
/
+22
*
Cleanup FDRE matching
Eddie Hung
2019-08-23
1
-45
/
+19
*
Oops don't need a finally block
Eddie Hung
2019-08-23
1
-5
/
+0
*
Keep track of bits in variable length chain, to check for taps
Eddie Hung
2019-08-23
1
-0
/
+12
*
Don't forget $dff has no EN
Eddie Hung
2019-08-23
1
-2
/
+4
*
Same for variable length
Eddie Hung
2019-08-23
1
-2
/
+10
*
Filter on en_port for fixed length
Eddie Hung
2019-08-23
1
-4
/
+24
*
Check clock is consistent
Eddie Hung
2019-08-23
1
-5
/
+25
*
Fix last_cell.D
Eddie Hung
2019-08-23
1
-2
/
+1
*
Revert "Add a unique argument to pmgen's nusers()"
Eddie Hung
2019-08-23
1
-8
/
+4
*
Revert "Fix polarity"
Eddie Hung
2019-08-23
1
-1
/
+1
*
Fix polarity
Eddie Hung
2019-08-23
1
-1
/
+1
*
Check for non unique nusers/fanouts
Eddie Hung
2019-08-23
1
-2
/
+2
*
Add a unique argument to pmgen's nusers()
Eddie Hung
2019-08-23
1
-4
/
+8
*
Update doc
Eddie Hung
2019-08-23
1
-12
/
+19
*
Remove (* init *) entry when consumed into SRL
Eddie Hung
2019-08-23
1
-2
/
+6
*
indo -> into
Eddie Hung
2019-08-23
1
-1
/
+1
*
Forgot to slice
Eddie Hung
2019-08-23
1
-1
/
+2
*
Cope with possibility that D could connect to Q on same cell
Eddie Hung
2019-08-23
1
-1
/
+1
*
xilinx_srl to use 'slice' features of pmgen for word level
Eddie Hung
2019-08-23
2
-32
/
+49
*
Merge remote-tracking branch 'origin/clifford/pmgen' into eddie/xilinx_srl
Eddie Hung
2019-08-23
4
-34
/
+279
|
\
|
*
Fix port hanlding in pmgen
Clifford Wolf
2019-08-23
1
-4
/
+3
|
*
Add pmgen slices and choices
Clifford Wolf
2019-08-23
4
-28
/
+276
*
|
Add doc
Eddie Hung
2019-08-22
1
-1
/
+14
*
|
Add copyright
Eddie Hung
2019-08-22
1
-0
/
+1
*
|
pmgen to also iterate over all module ports
Eddie Hung
2019-08-22
1
-2
/
+4
*
|
Remove output_bits
Eddie Hung
2019-08-22
2
-16
/
+7
*
|
Forgot to set ud_variable.minlen
Eddie Hung
2019-08-22
1
-0
/
+1
*
|
Do not run xilinx_srl_pm in fixed loop
Eddie Hung
2019-08-22
1
-28
/
+24
*
|
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
Eddie Hung
2019-08-22
1
-1
/
+1
|
\
|
|
*
Fix test_pmgen deps
Miodrag Milanovic
2019-08-21
1
-1
/
+1
*
|
Reuse var
Eddie Hung
2019-08-21
1
-1
/
+1
*
|
Revert "Trim shiftx_width when upper bits are 1'bx"
Eddie Hung
2019-08-21
1
-6
/
+1
*
|
Trim shiftx_width when upper bits are 1'bx
Eddie Hung
2019-08-21
1
-1
/
+6
*
|
Add comment
Eddie Hung
2019-08-21
1
-0
/
+4
*
|
Add variable length support to xilinx_srl
Eddie Hung
2019-08-21
2
-14
/
+164
*
|
Rename pattern to fixed
Eddie Hung
2019-08-21
2
-10
/
+10
*
|
attribute -> attr
Eddie Hung
2019-08-21
1
-4
/
+4
*
|
Use Cell::has_keep_attribute()
Eddie Hung
2019-08-21
1
-4
/
+4
*
|
xilinx_srl to support FDRE and FDRE_1
Eddie Hung
2019-08-21
2
-10
/
+73
*
|
Fix polarity of EN_POL
Eddie Hung
2019-08-21
1
-2
/
+2
*
|
Add CLKPOL == 0
Eddie Hung
2019-08-21
1
-0
/
+2
*
|
Reject if not minlen from inside pattern matcher
Eddie Hung
2019-08-21
2
-8
/
+11
*
|
Get wire via SigBit
Eddie Hung
2019-08-21
1
-4
/
+4
*
|
Respect \keep on cells or wires
Eddie Hung
2019-08-21
1
-2
/
+10
*
|
Add init support
Eddie Hung
2019-08-21
1
-2
/
+11
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