| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | xilinx_srl to support FDRE and FDRE_1 | Eddie Hung | 2019-08-21 | 1 | -4/+50 |
| * | Reject if not minlen from inside pattern matcher | Eddie Hung | 2019-08-21 | 1 | -1/+2 |
| * | Get wire via SigBit | Eddie Hung | 2019-08-21 | 1 | -4/+4 |
| * | Respect \keep on cells or wires | Eddie Hung | 2019-08-21 | 1 | -2/+10 |
| * | Initial progress on xilinx_srl | Eddie Hung | 2019-08-21 | 1 | -0/+92 |
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index : iCE40/yosys | |
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