iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Squelch trailing whitespace	Larry Doolittle	2017-04-12	1	-3/+3
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*	Disable opt_merge for $anyseq and $anyconst	Clifford Wolf	2017-02-28	1	-0/+3
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*	Add $live and $fair cell types, add support for s_eventually keyword	Clifford Wolf	2017-02-25	1	-1/+1
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*	Fixed some "used uninitialized" warnings in opt_expr	Clifford Wolf	2017-02-11	1	-1/+2
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*	Add optimization of (a && 1'b1) and (a \|\| 1'b0)	Clifford Wolf	2017-02-11	1	-7/+22
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*	Fix issue #306, "Bug in opt -full"	C-Elegans	2017-02-10	1	-1/+19
\| \| \| \| \| \|	Add check for whether the high bit in the constant expression is greater than the width of the variable, and optimizes that to a constant 1 or 0
*	Fix handling of init attributes with strange width	Clifford Wolf	2017-02-09	2	-3/+9
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*	Add $cover cell type and SVA cover() support	Clifford Wolf	2017-02-04	1	-1/+1
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*	Fix indenting and log messages in code merged from opt_compare_pr	Clifford Wolf	2017-01-31	1	-102/+120
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*	Merge branch 'opt_compare_pr' of https://github.com/C-Elegans/yosys into ↵	Clifford Wolf	2017-01-31	1	-1/+103
\|\ \| \| \| \| \| \|	C-Elegans-opt_compare_pr
\| *	Refactor and generalize the comparision optimization	C-Elegans	2017-01-30	1	-22/+42
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Generalizes the optimization to: a < C, a >= C, C > a, C <= a
\| *	Do not use b.as_int() in calculation of bit set	C-Elegans	2017-01-21	1	-8/+29
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\| *	Optimize compares to powers of 2	C-Elegans	2017-01-16	4	-81/+61
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Remove opt_compare and put comparison pass in opt_expr assuming a [7:0] is unsigned a >= (1<<x) becomes \|a[7:x] a < (1<<x) becomes !a[7:x] Additionally: a >= 0 becomes constant true, a < 0 becomes constant false delete opt_compare.cc revert opt.cc to commit b7cfb7dbd (remove opt_compare step)
\| *	Fix issue #269, optimize signed compare with 0	C-Elegans	2017-01-15	3	-0/+81
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	add opt_compare pass and add it to opt for a < 0: if a is signed, replace with a[max_bit-1] for a >= 0: if a is signed, replace with ~a[max_bit-1]
* \|	Improve opt_rmdff support for $dlatch cells	Clifford Wolf	2017-01-31	1	-4/+22
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*	Added opt_rmdff support for $ff cells	Clifford Wolf	2016-10-14	1	-5/+13
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*	Added "opt_rmdff -keepdc"	Clifford Wolf	2016-09-30	2	-7/+20
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*	Improved init spec handling in opt_rmdff, modernized the code a bit	Clifford Wolf	2016-08-30	1	-39/+82
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*	Removed $predict again	Clifford Wolf	2016-08-28	1	-1/+1
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*	Added "wreduce -memx"	Clifford Wolf	2016-08-20	1	-3/+14
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*	Optimize memory address port width in wreduce and memory_collect, not ↵	Clifford Wolf	2016-08-19	1	-0/+18
\| \| \| \|	verilog front-end
*	After reading the SV spec, using non-standard predict() instead of expect()	Clifford Wolf	2016-07-21	1	-1/+1
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*	Added basic support for $expect cells	Clifford Wolf	2016-07-13	1	-1/+1
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*	Added opt_expr support for div/mod by power-of-two	Clifford Wolf	2016-05-29	1	-0/+69
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*	Connections between inputs and inouts are driven by the input	Clifford Wolf	2016-04-26	1	-0/+3
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*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	9	-12/+12
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*	Fixed performance bug in "share" pass	Clifford Wolf	2016-04-21	1	-2/+51
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*	Improvements in opt_expr	Clifford Wolf	2016-04-21	1	-12/+62
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*	Improved opt_merge support for $pmux cells	Clifford Wolf	2016-03-31	1	-4/+46
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*	Typo fixes in opt_expr and opt_merge	Clifford Wolf	2016-03-31	2	-2/+2
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*	Renamed opt_share to opt_merge	Clifford Wolf	2016-03-31	3	-18/+18
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*	Renamed opt_const to opt_expr	Clifford Wolf	2016-03-31	3	-52/+53
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*	Fixed typo in log message	Andrew Zonenberg	2016-03-30	1	-1/+1
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*	Use alphanumerical order instead of idstring idx in opt_clean compare_signals()	Clifford Wolf	2016-02-02	1	-1/+1
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*	Improvements in wreduce	Clifford Wolf	2015-10-31	1	-0/+25
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*	Import more std:: stuff into Yosys namespace	Clifford Wolf	2015-10-25	3	-33/+33
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*	Fixed handling of driver-driver conflicts in wreduce	Clifford Wolf	2015-10-24	1	-8/+16
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*	Bugfixes in handling of "keep" attribute on wires	Clifford Wolf	2015-10-15	2	-2/+8
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*	Added wreduce $mul support and fixed signed $mul opt_const bug	Clifford Wolf	2015-09-25	2	-5/+37
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*	Added detection of "mux inverter" chains in opt_const	Clifford Wolf	2015-09-18	1	-0/+2
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*	Fixed sharing of $memrd cells	Clifford Wolf	2015-09-12	1	-0/+4
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*	gcc-4.6 build fixes	Clifford Wolf	2015-09-01	1	-2/+2
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*	Properly clean up unused "init" attributes	Clifford Wolf	2015-08-18	1	-2/+18
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*	Fixed opt_clean handling of inout ports	Clifford Wolf	2015-08-16	1	-2/+2
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*	Spell check (by Larry Doolittle)	Clifford Wolf	2015-08-14	2	-2/+2
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*	Improved handling of "keep" attributes in hierarchical designs in opt_clean	Clifford Wolf	2015-08-12	1	-25/+57
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*	Merge pull request #70 from gaomy3832/bugfix	Clifford Wolf	2015-08-12	1	-0/+10
\|\ \| \| \| \|	Remove unused blackbox modules in opt_clean.
\| *	Remove unused blackbox modules in opt_clean.	Mingyu Gao	2015-08-11	1	-0/+10
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\| *	Bugfix for cell hash cache option in opt_share.	Mingyu Gao	2015-08-10	1	-0/+2
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* \|	Bugfix for cell hash cache option in opt_share.	Mingyu Gao	2015-08-11	1	-0/+2
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