| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Various fixes for memories with offsets | Clifford Wolf | 2015-02-14 | 2 | -5/+17 |
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| * | Added $meminit support to "memory" command | Clifford Wolf | 2015-02-14 | 3 | -30/+69 |
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| * | Added onehot attribute | Clifford Wolf | 2015-02-04 | 1 | -0/+13 |
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| * | Fixed typos found by lintian | Ruben Undheim | 2015-02-01 | 1 | -2/+2 |
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| * | Refactoring of memory_bram and xilinx brams | Clifford Wolf | 2015-01-18 | 1 | -204/+407 |
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| * | memory_bram hotfix for memories with width 1 | Clifford Wolf | 2015-01-06 | 1 | -3/+3 |
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| * | removed old debug code | Clifford Wolf | 2015-01-06 | 1 | -1/+0 |
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| * | Towards Xilinx bram support | Clifford Wolf | 2015-01-06 | 1 | -1/+0 |
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| * | Towards Xilinx bram support | Clifford Wolf | 2015-01-06 | 1 | -1/+1 |
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| * | Towards Xilinx bram support | Clifford Wolf | 2015-01-05 | 1 | -0/+3 |
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| * | Towards Xilinx bram support | Clifford Wolf | 2015-01-04 | 1 | -3/+4 |
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| * | Added memory_bram "shuffle_enable" feature | Clifford Wolf | 2015-01-04 | 1 | -1/+113 |
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| * | Removed left over debug code from memory_bram | Clifford Wolf | 2015-01-04 | 1 | -2/+2 |
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| * | Added "memory -bram" | Clifford Wolf | 2015-01-03 | 1 | -2/+11 |
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| * | Added memory_bram 'or_next_if_better' feature | Clifford Wolf | 2015-01-03 | 1 | -42/+156 |
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| * | memory_bram transp support | Clifford Wolf | 2015-01-03 | 1 | -4/+22 |
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| * | Progress in memory_bram | Clifford Wolf | 2015-01-03 | 1 | -11/+5 |
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| * | Added proper clkpol support to memory_bram | Clifford Wolf | 2015-01-02 | 1 | -4/+32 |
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| * | Progress in memory_bram | Clifford Wolf | 2015-01-02 | 1 | -3/+6 |
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| * | Progress in memory_bram | Clifford Wolf | 2015-01-02 | 1 | -1/+10 |
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| * | Progress in memory_bram | Clifford Wolf | 2015-01-01 | 1 | -22/+207 |
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| * | Progress in memory_bram | Clifford Wolf | 2015-01-01 | 1 | -37/+145 |
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| * | Progress in memory_bram | Clifford Wolf | 2014-12-31 | 1 | -7/+115 |
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| * | Added memory_bram (not functional yet) | Clifford Wolf | 2014-12-31 | 2 | -0/+286 |
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| * | More dict/pool related changes | Clifford Wolf | 2014-12-27 | 1 | -2/+2 |
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| * | Renamed extend() to extend_xx(), changed most users to extend_u0() | Clifford Wolf | 2014-12-24 | 1 | -12/+12 |
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| * | Renamed SIZE() to GetSize() because of name collision on Win32 | Clifford Wolf | 2014-10-10 | 1 | -5/+5 |
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| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 6 | -12/+32 |
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| * | Fixed $memwr/$memrd order in memory_dff | Clifford Wolf | 2014-09-16 | 1 | -4/+6 |
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| * | Corrected spelling mistakes found by lintian | Ruben Undheim | 2014-09-06 | 1 | -1/+1 |
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| * | Improved write address decoder generation memory_map | Clifford Wolf | 2014-08-30 | 1 | -16/+28 |
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| * | Using worker class in memory_map | Clifford Wolf | 2014-08-30 | 1 | -226/+231 |
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| * | Various improvements in memory_dff pass | Clifford Wolf | 2014-08-06 | 1 | -21/+22 |
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| * | No implicit conversion from IdString to anything else | Clifford Wolf | 2014-08-02 | 1 | -1/+1 |
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| * | More cleanups related to RTLIL::IdString usage | Clifford Wolf | 2014-08-02 | 3 | -9/+9 |
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| * | Added ModIndex helper class, some changes to RTLIL::Monitor | Clifford Wolf | 2014-08-01 | 1 | -3/+2 |
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| * | Renamed modwalker.h to modtools.h | Clifford Wolf | 2014-07-31 | 1 | -5/+6 |
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| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 5 | -128/+128 |
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| * | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 | 4 | -4/+4 |
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| * | Added $shift and $shiftx cell types (needed for correct part select behavior) | Clifford Wolf | 2014-07-29 | 1 | -0/+2 |
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| * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 4 | -15/+11 |
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| * | Using new obj iterator API in a few places | Clifford Wolf | 2014-07-27 | 1 | -15/+11 |
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| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 5 | -5/+5 |
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| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 5 | -9/+9 |
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| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 2 | -2/+2 |
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| * | Changed a lot of code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 2 | -46/+16 |
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| * | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 2 | -17/+29 |
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| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 5 | -128/+128 |
| | | | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' | ||||
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 5 | -128/+128 |
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| * | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 4 | -59/+20 |
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