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| author | Clifford Wolf <clifford@clifford.at> | 2015-01-06 23:59:53 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-06 23:59:53 +0100 |
| commit | b26590f8ab2bc77b6209a98240d465af7d3ee266 (patch) | |
| tree | 2e121f2fff342d7f5dffdc012b92aedd59f74c82 /passes/memory | |
| parent | 08c13f635cb59f701b51a14caf608c503b6eecb1 (diff) | |
| download | yosys-b26590f8ab2bc77b6209a98240d465af7d3ee266.tar.gz yosys-b26590f8ab2bc77b6209a98240d465af7d3ee266.tar.bz2 yosys-b26590f8ab2bc77b6209a98240d465af7d3ee266.zip | |
memory_bram hotfix for memories with width 1
Diffstat (limited to 'passes/memory')
| -rw-r--r-- | passes/memory/memory_bram.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 8c7338b91..b212e92ed 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -294,10 +294,10 @@ bool replace_cell(Cell *cell, const rules_t::bram_t &bram, const rules_t::match_ SigSpec rd_data = cell->getPort("\\RD_DATA"); SigSpec rd_addr = cell->getPort("\\RD_ADDR"); - if (match.shuffle_enable) + if (match.shuffle_enable && bram.dbits >= match.shuffle_enable*2) { int bucket_size = bram.dbits / match.shuffle_enable; - log(" Shuffle enable and data bit to accommodate enable buckets of size %d..\n", bucket_size); + log(" Shuffle bit order to accommodate enable buckets of size %d..\n", bucket_size); // extract unshuffled data/enable bits @@ -363,7 +363,7 @@ bool replace_cell(Cell *cell, const rules_t::bram_t &bram, const rules_t::match_ } } - log(" Results of enable shuffling:"); + log(" Results of bit order shuffling:"); for (int v : shuffle_map) log(" %d", v); log("\n"); |