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* Remove clkpartEddie Hung2019-12-052-309/+0
* Use pool instead of std::set for determinismEddie Hung2019-12-011-1/+1
* Use pool<> not std::set<> for determinismEddie Hung2019-12-011-4/+4
* Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dffEddie Hung2019-11-281-1/+1
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| * Move \init signal for non-port signals as long as internally drivenEddie Hung2019-11-281-1/+1
| * Fix multiple driver issueEddie Hung2019-11-271-2/+7
* | Fix multiple driver issueEddie Hung2019-11-271-2/+7
* | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dffEddie Hung2019-11-271-7/+3
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| * Do not replace constants with same wireEddie Hung2019-11-271-7/+3
* | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dffEddie Hung2019-11-271-47/+71
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| * CleanupEddie Hung2019-11-271-5/+3
| * Check for nullptrEddie Hung2019-11-271-1/+1
| * Stray log_dumpEddie Hung2019-11-271-1/+0
| * Revert "submod to bitty rather bussy, for bussy wires used as input and output"Eddie Hung2019-11-271-40/+71
| * Promote output wires in sigmap so that can be detectedEddie Hung2019-11-261-8/+4
| * Fix submod -hiddenEddie Hung2019-11-261-5/+6
| * Add -hidden option to submodEddie Hung2019-11-261-11/+25
| * Update docs with bullet pointsEddie Hung2019-11-261-10/+9
| * Move \init from source wire to submod if output portEddie Hung2019-11-251-0/+7
* | Fix submod -hiddenEddie Hung2019-11-261-5/+6
* | clkpart to use 'submod -hidden'Eddie Hung2019-11-261-1/+1
* | Add -hidden option to submodEddie Hung2019-11-261-20/+40
* | clkpart to analyse async flops tooEddie Hung2019-11-251-0/+8
* | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dffEddie Hung2019-11-231-2/+3
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| * | More oopsiesEddie Hung2019-11-231-2/+3
* | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dffEddie Hung2019-11-231-13/+27
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| * | Print ".en=" only if there is an enable signalEddie Hung2019-11-231-1/+1
| * | Escape IdStringsEddie Hung2019-11-231-3/+2
| * | More sane naming of submodEddie Hung2019-11-231-2/+2
| * | Add -set_attr option, -unpart to take attr nameEddie Hung2019-11-231-10/+25
* | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dffEddie Hung2019-11-231-18/+34
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| * | Do not use log_signal() for empty SigSpec to prevent "{ }"Eddie Hung2019-11-221-2/+4
| * | Call submod once, more meaningful submod names, ignore largest domainEddie Hung2019-11-221-18/+32
* | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dffEddie Hung2019-11-222-0/+270
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| * Move clkpart into passes/hierarchyEddie Hung2019-11-222-0/+270
* | submod to bitty rather bussy, for bussy wires used as input and outputEddie Hung2019-11-221-48/+39
* | Constant driven signals are also an input to submodulesEddie Hung2019-11-221-2/+10
* | OopsEddie Hung2019-11-221-1/+0
* | sigmap(wire) should inherit port_output status of POsEddie Hung2019-11-221-1/+19
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* Adopt @cliffordwolf's suggestionEddie Hung2019-09-031-10/+3
* -auto-top should check $abstract (deferred) modules with (* top *)Eddie Hung2019-08-281-0/+31
* stoi -> atoiEddie Hung2019-08-071-3/+3
* IdString::str().substr() -> IdString::substr()Eddie Hung2019-08-061-1/+1
* Fix typosEddie Hung2019-08-061-5/+5
* Use IdString::begins_with()Eddie Hung2019-08-061-11/+9
* Use input default values in hierarchy passClifford Wolf2019-06-191-0/+38
* Refactor hierarchy wand/wor handlingClifford Wolf2019-05-281-102/+143
* move wand/wor resolution into hierarchy passStefan Biereigel2019-05-271-1/+77
* Add "hierarchy -chparam" support for non-verific top modulesClifford Wolf2019-05-031-12/+35
* log_warning_noprefix -> log_warning as per reviewEddie Hung2019-05-031-1/+1