| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Support importing verilog configurations using Verific | Miodrag Milanovic | 2022-11-25 | 1 | -1/+1 |
| * | Makes sure to set initial_top when change, fixes #3462 | Miodrag Milanovic | 2022-08-26 | 1 | -0/+1 |
| * | add hierarchy -smtcheck | Jacob Lifshay | 2022-06-22 | 1 | -7/+16 |
| * | Reorder steps in -auto-top to fix synth command, fixes #3261 | Miodrag Milanovic | 2022-04-05 | 1 | -13/+13 |
| * | verilog: use derived module info to elaborate cell connections | Zachary Snow | 2021-10-25 | 1 | -0/+4 |
| * | Split out logic for reprocessing an AstModule | Rupert Swarbrick | 2021-10-25 | 1 | -1/+1 |
| * | Use new read_id_num helper function elsewhere in hierarchy.cc | Rupert Swarbrick | 2021-07-20 | 1 | -5/+6 |
| * | Extract connection checking logic from expand_module in hierarchy.cc | Rupert Swarbrick | 2021-07-20 | 1 | -23/+64 |
| * | Extract missing module support in hierarchy.cc to a helper function | Rupert Swarbrick | 2021-07-14 | 1 | -44/+68 |
| * | Move interface expansion in hierarchy.cc into a helper class | Rupert Swarbrick | 2021-06-16 | 1 | -100/+189 |
| * | Fixing old e-mail addresses and deadnames | Claire Xenia Wolf | 2021-06-08 | 1 | -1/+1 |
| * | Sign extend port connections where necessary | Zachary Snow | 2020-12-18 | 1 | -2/+6 |
| * | Validate parameters only when they are used | Miodrag Milanovic | 2020-09-25 | 1 | -5/+7 |
| * | Replace "ILANG" with "RTLIL" everywhere. | whitequark | 2020-08-26 | 1 | -1/+1 |
| * | Use C++11 final/override keywords. | whitequark | 2020-06-18 | 1 | -2/+2 |
| * | Merge pull request #2089 from rswarbrick/modports | clairexen | 2020-06-08 | 1 | -13/+6 |
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| | * | Simplify a modport check in hierarchy.cc | Rupert Swarbrick | 2020-05-26 | 1 | -13/+6 |
| * | | Fix small typos in documentation for hierarchy command | Rupert Swarbrick | 2020-05-28 | 1 | -2/+2 |
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| * | hierarchy: Convert positional parameters to named. | Marcelina Kościelnicka | 2020-04-21 | 1 | -3/+27 |
| * | kernel: big fat patch to use more ID::*, otherwise ID(*) | Eddie Hung | 2020-04-02 | 1 | -18/+18 |
| * | kernel: use more ID::* | Eddie Hung | 2020-04-02 | 1 | -20/+20 |
| * | Fix double deletion in `passes/hierarchy/hierarchy.cc`. | Alberto Gonzalez | 2020-03-30 | 1 | -1/+0 |
| * | Clean up pseudo-private member usage in `passes/hierarchy/hierarchy.cc`. | Alberto Gonzalez | 2020-03-19 | 1 | -68/+63 |
| * | sv: Improve handling of wildcard port connections | David Shah | 2020-02-02 | 1 | -3/+3 |
| * | hierarchy: Correct handling of wildcard port connections with default values | David Shah | 2020-02-02 | 1 | -7/+14 |
| * | hierarchy: Resolve SV wildcard port connections | David Shah | 2020-02-02 | 1 | -3/+62 |
| * | Adopt @cliffordwolf's suggestion | Eddie Hung | 2019-09-03 | 1 | -10/+3 |
| * | -auto-top should check $abstract (deferred) modules with (* top *) | Eddie Hung | 2019-08-28 | 1 | -0/+31 |
| * | stoi -> atoi | Eddie Hung | 2019-08-07 | 1 | -3/+3 |
| * | IdString::str().substr() -> IdString::substr() | Eddie Hung | 2019-08-06 | 1 | -1/+1 |
| * | Fix typos | Eddie Hung | 2019-08-06 | 1 | -5/+5 |
| * | Use IdString::begins_with() | Eddie Hung | 2019-08-06 | 1 | -11/+9 |
| * | Use input default values in hierarchy pass | Clifford Wolf | 2019-06-19 | 1 | -0/+38 |
| * | Refactor hierarchy wand/wor handling | Clifford Wolf | 2019-05-28 | 1 | -102/+143 |
| * | move wand/wor resolution into hierarchy pass | Stefan Biereigel | 2019-05-27 | 1 | -1/+77 |
| * | Add "hierarchy -chparam" support for non-verific top modules | Clifford Wolf | 2019-05-03 | 1 | -12/+35 |
| * | log_warning_noprefix -> log_warning as per review | Eddie Hung | 2019-05-03 | 1 | -1/+1 |
| * | WIP -chparam support for hierarchy when verific | Eddie Hung | 2019-05-03 | 1 | -7/+24 |
| * | Add "whitebox" attribute, add "read_verilog -wb" | Clifford Wolf | 2019-04-18 | 1 | -5/+5 |
| * | Only run derive on blackbox modules when ports have dynamic size | Clifford Wolf | 2019-03-02 | 1 | -1/+1 |
| * | Minor changes ontop of 71bcc4c: Remove hierarchy warning that is redundant to... | Clifford Wolf | 2019-02-24 | 1 | -5/+1 |
| * | Address requested changes - don't require non-$ name. | Jim Lawson | 2019-02-22 | 1 | -7/+7 |
| * | Fix normal (non-array) hierarchy -auto-top. | Jim Lawson | 2019-02-19 | 1 | -9/+9 |
| * | Define basic_cell_type() function and use it to derive the cell type for arra... | Jim Lawson | 2019-02-15 | 1 | -10/+40 |
| * | Fix typographical and grammatical errors and inconsistencies. | whitequark | 2019-01-02 | 1 | -1/+1 |
| * | Refactor code to avoid code duplication + added comments | Ruben Undheim | 2018-10-20 | 1 | -2/+5 |
| * | Support for SystemVerilog interfaces as a port in the top level module + test... | Ruben Undheim | 2018-10-20 | 1 | -5/+36 |
| * | Documentation improvements etc. | Ruben Undheim | 2018-10-13 | 1 | -27/+38 |
| * | Support for 'modports' for System Verilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -1/+13 |
| * | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -7/+165 |
