iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	add option to fsm_detect to ignore self-resetting	N. Engelhardt	2023-01-30	1	-7/+22
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*	mention prerequisites in fsm_detect and fsm help	N. Engelhardt	2022-11-21	1	-0/+9
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*	Add the $anyinit cell and the formalff pass	Jannis Harder	2022-08-16	1	-0/+1
\| \| \| \| \| \| \|	These can be used to protect undefined flip-flop initialization values from optimizations that are not sound for formal verification and can help mapping all solver-provided values in witness traces for flows that use different backends simultaneously.
*	Fixing old e-mail addresses and deadnames	Claire Xenia Wolf	2021-06-08	1	-1/+1
\| \| \| \| \| \| \| \|	s/((Claire\|Xen\|Xenia\|Clifford)\s+)+(Wolf\|Xen)\s+<(claire\|clifford)@(symbioticeda.com\|clifford.at\|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina\|Nak\|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com\|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave\|david)@(symbioticeda.com\|yosyshq.com\|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag\|micko)@(symbioticeda.com\|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
*	Use C++11 final/override keywords.	whitequark	2020-06-18	1	-2/+2
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*	kernel: big fat patch to use more ID::, otherwise ID()	Eddie Hung	2020-04-02	1	-25/+21
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*	kernel: use more ID::*	Eddie Hung	2020-04-02	1	-13/+13
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*	fsm_detect: Add a cache to avoid excessive CPU usage for big mux networks.	Marcin Kościelnicki	2020-01-14	1	-9/+17
\| \| \| \|	Fixes #1634.
*	Update fsm_detect bugfix	Clifford Wolf	2019-11-12	1	-3/+4
\| \| \| \|	Signed-off-by: Clifford Wolf <clifford@clifford.at>
*	Bugfix in fsm_detect	Clifford Wolf	2019-11-12	1	-6/+9
\| \| \| \|	Signed-off-by: Clifford Wolf <clifford@clifford.at>
*	Fix typographical and grammatical errors and inconsistencies.	whitequark	2019-01-02	1	-4/+4
\| \| \| \| \| \| \| \| \| \| \| \|	The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
\| \| \| \| \| \| \| \| \|	o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -- c++ -- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
*	Squelch trailing whitespace	Larry Doolittle	2017-04-12	1	-2/+2
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*	Further improved fsm_detect output, attempt to detect self-resetting circuits	Clifford Wolf	2016-07-09	1	-6/+68
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*	Added printing of some warning messages to fsm_detect	Clifford Wolf	2016-07-09	1	-14/+61
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*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
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*	Do not detect fsm state registers with init attribute	Clifford Wolf	2015-09-21	1	-0/+2
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*	Added $logic_not handling to fsm_detect	Clifford Wolf	2015-09-18	1	-0/+2
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*	Bugfix in fsm_detect for complex muxtrees	Clifford Wolf	2015-08-18	1	-15/+23
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*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
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*	Added log_warning() API	Clifford Wolf	2014-11-09	1	-1/+1
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*	namespace Yosys	Clifford Wolf	2014-09-27	1	-0/+4
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*	RIP $safe_pmux	Clifford Wolf	2014-08-14	1	-1/+1
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-1/+1
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-7/+7
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-1/+1
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-2/+2
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*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26	1	-1/+1
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-9/+9
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-9/+9
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*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-2/+2
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-2/+2
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*	Fixes in fsm detect/extract for better detection of non-fsm circuits	Clifford Wolf	2013-12-06	1	-1/+1
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*	Added detection for endless recursion in fsm_detect pass	Clifford Wolf	2013-10-30	1	-4/+15
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*	fixed typos	Johann Glaser	2013-03-18	1	-3/+3
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*	Added help messages for fsm_* passes	Clifford Wolf	2013-03-01	1	-2/+22
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*	initial import	Clifford Wolf	2013-01-05	1	-0/+160