| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -2/+2 |
| * | Added wire start_offset and upto handling to splitnets cmd | Clifford Wolf | 2016-11-23 | 1 | -2/+8 |
| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 |
| * | Fixed "splitnets -ports" for hierarchical designs | Clifford Wolf | 2015-12-22 | 1 | -0/+57 |
| * | Import more std:: stuff into Yosys namespace | Clifford Wolf | 2015-10-25 | 1 | -2/+2 |
| * | Fixed port ordering in "splitnets" cmd | Clifford Wolf | 2015-09-01 | 1 | -7/+18 |
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -3/+3 |
| * | Preserve important attributes in splitnets | Clifford Wolf | 2015-04-29 | 1 | -0/+13 |
| * | Renamed hashmap.h to hashlib.h, some related improvements | Clifford Wolf | 2014-12-28 | 1 | -1/+1 |
| * | More hashtable finetuning | Clifford Wolf | 2014-12-27 | 1 | -1/+1 |
| * | Replaced std::unordered_set (nodict) with Yosys::pool | Clifford Wolf | 2014-12-26 | 1 | -1/+1 |
| * | Added Yosys::{dict,nodict,vector} container types | Clifford Wolf | 2014-12-26 | 1 | -1/+1 |
| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -0/+4 |
| * | Corrected spelling mistakes found by lintian | Ruben Undheim | 2014-09-06 | 1 | -1/+1 |
| * | Added module->uniquify() | Clifford Wolf | 2014-08-16 | 1 | -4/+1 |
| * | More cleanups related to RTLIL::IdString usage | Clifford Wolf | 2014-08-02 | 1 | -1/+1 |
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
| * | Changed a lot of code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 1 | -20/+18 |
| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -1/+1 |
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -1/+1 |
| * | Removed RTLIL::SigSpec::optimize() | Clifford Wolf | 2014-07-23 | 1 | -1/+1 |
| * | Fixed all users of SigSpec::chunks_rw() and removed it | Clifford Wolf | 2014-07-23 | 1 | -5/+3 |
| * | SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created... | Clifford Wolf | 2014-07-22 | 1 | -1/+1 |
| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -2/+2 |
| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -2/+2 |
| * | Fixed use of selection in splitnets command | Clifford Wolf | 2014-02-16 | 1 | -1/+1 |
| * | Added log_header() to splitnets | Clifford Wolf | 2014-02-07 | 1 | -0/+2 |
| * | Added "splitnets -driver" | Clifford Wolf | 2014-01-03 | 1 | -29/+96 |
| * | Added -format option to splitnets | Clifford Wolf | 2013-10-29 | 1 | -1/+16 |
| * | Added splitnets command | Clifford Wolf | 2013-06-18 | 1 | -0/+108 |
