| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -3/+3 |
| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -3/+3 |
| * | Changed a lot of code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 1 | -4/+1 |
| * | Added RTLIL::Cell::has(portname) | Clifford Wolf | 2014-07-26 | 1 | -1/+1 |
| * | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 1 | -1/+1 |
| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -2/+2 |
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -2/+2 |
| * | Renamed "placeholder" to "blackbox" | Clifford Wolf | 2013-11-22 | 1 | -2/+2 |
| * | Fixed a bug in "add -global_input" | Clifford Wolf | 2013-11-21 | 1 | -16/+17 |
| * | Added "add" command (only wires for now) | Clifford Wolf | 2013-11-20 | 1 | -0/+154 |
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