| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Renamed temp module generated by "abc" pass from "logic" to "netlist" | Clifford Wolf | 2013-11-19 | 1 | -1/+1 |
| * | Fixed abc pass blif parser for constant bits | Clifford Wolf | 2013-11-13 | 1 | -18/+57 |
| * | Added $lut cells and abc lut mapping support | Clifford Wolf | 2013-07-23 | 1 | -0/+168 |
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index : iCE40/yosys | |
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