iCE40/yosys - clone of https://github.com/YosysHQ/yosys

	Commit message (Collapse)	Author	Age	Files	Lines
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*	SigSpec refactoring: renamed the SigSpec members to chunks_ and width_ and ↵	Clifford Wolf	2014-07-22	2	-152/+158
\| \| \| \|	added accessor functions
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	6	-244/+247
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*	Added support for scripts with labels	Clifford Wolf	2014-07-21	1	-11/+74
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*	Replaced depricated NEW_WIRE macro with module->addWire() calls	Clifford Wolf	2014-07-21	1	-3/+0
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*	Removed deprecated module->new_wire()	Clifford Wolf	2014-07-21	2	-20/+11
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*	Bugfix in satgen for cells with wider in- than outputs.	Clifford Wolf	2014-07-21	1	-1/+9
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*	Added module->remove(), module->addWire(), module->addCell(), cell->check()	Clifford Wolf	2014-07-21	2	-8/+44
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*	Added log_ping()	Clifford Wolf	2014-07-21	1	-0/+1
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*	Added call_on_selection() and call_on_module() API	Clifford Wolf	2014-07-20	2	-6/+35
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*	Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion	Clifford Wolf	2014-07-20	2	-3/+11
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*	Added SIZE() macro	Clifford Wolf	2014-07-20	1	-0/+2
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*	Added log_cell()	Clifford Wolf	2014-07-20	2	-0/+17
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*	Fixed log_id() memory corruption	Clifford Wolf	2014-07-19	2	-5/+10
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*	Added ModWalker helper class	Clifford Wolf	2014-07-19	1	-0/+298
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*	Some "const" cleanups in SigMap	Clifford Wolf	2014-07-19	1	-4/+4
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*	Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit>	Clifford Wolf	2014-07-18	1	-0/+1
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*	Added function-like cell creation helpers	Clifford Wolf	2014-07-18	2	-73/+158
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*	Added log_id() helper function	Clifford Wolf	2014-07-18	1	-0/+8
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*	Fixed RTLIL::SigSpec::append_bit() for appending constants	Clifford Wolf	2014-07-17	1	-2/+3
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*	Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal	Clifford Wolf	2014-07-16	1	-2/+2
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*	Use "verilog -sv" to parse .sv files	Clifford Wolf	2014-07-11	1	-0/+2
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*	Add support for cell arrays	Clifford Wolf	2014-06-07	1	-1/+2
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*	Improved error message for options after front-end filename arguments	Clifford Wolf	2014-06-04	1	-0/+4
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*	workaround for OpenBSD 'stdout' implementation	Clifford Wolf	2014-05-03	1	-1/+2
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*	workaround for OpenBSD 'stdin' implementation	Clifford Wolf	2014-05-02	1	-1/+2
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*	Added support for dlatchsr cells	Clifford Wolf	2014-03-31	3	-1/+71
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*	Fixed typo in RTLIL::Module::addAdff()	Clifford Wolf	2014-03-17	1	-1/+1
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*	Fixed typo in RTLIL::Module::{addSshl,addSshr}	Clifford Wolf	2014-03-15	1	-2/+2
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*	Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() API	Clifford Wolf	2014-03-15	2	-1/+61
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*	Added log_dump() support for generic pointers	Clifford Wolf	2014-03-14	1	-0/+3
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*	Progress in Verific bindings	Clifford Wolf	2014-03-14	1	-1/+1
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*	Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate API	Clifford Wolf	2014-03-14	2	-0/+48
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*	Hotfix for kernel/compatibility.h	Clifford Wolf	2014-03-13	1	-1/+2
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*	Merged OSX fixes from Siesh1oo with some modifications	Clifford Wolf	2014-03-13	5	-2/+176
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*	- kernel/register.h, kernel/driver.cc: refactor ↵	Siesh1oo	2014-03-12	2	-34/+39
\| \| \| \| \| \| \|	rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname(). This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems. - passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics.
*	Added libs/minisat (copy of minisat git master)	Clifford Wolf	2014-03-12	1	-6/+1
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*	Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys	Clifford Wolf	2014-03-11	3	-0/+18
\| \| \| \|	(see https://github.com/cliffordwolf/yosys/pull/28)
*	Fixed a typo in RTLIL::Module::addReduce...	Clifford Wolf	2014-03-10	1	-5/+5
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*	Added RTLIL::Module::add... helper methods	Clifford Wolf	2014-03-10	2	-0/+293
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*	Fixed use of frozen literals in SatGen	Clifford Wolf	2014-03-06	1	-3/+2
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*	Strictly zero-extend unsigned A-inputs of shift operations	Clifford Wolf	2014-03-06	2	-3/+3
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*	Fixed const folding of $bu0 cells	Clifford Wolf	2014-02-27	1	-1/+1
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*	Added support for $bu0 to SatGen	Clifford Wolf	2014-02-26	1	-4/+4
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*	Added support for Minisat::SimpSolver + ezSAT frezze() API	Clifford Wolf	2014-02-23	1	-0/+1
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*	Fixed small memory leak in Pass::call()	Clifford Wolf	2014-02-23	1	-1/+4
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*	Added "design -push" and "design -pop"	Clifford Wolf	2014-02-20	1	-0/+4
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*	Improved checking of internal cell conventions	Clifford Wolf	2014-02-08	1	-8/+17
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*	Added $slice and $concat to CellTypes list	Clifford Wolf	2014-02-07	1	-0/+2
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*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07	3	-4/+54
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*	Stronger checking of internal cells	Clifford Wolf	2014-02-07	1	-29/+37
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