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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-21 12:41:29 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-21 12:42:02 +0200 |
| commit | 361e0d62ffd90b87c94bfc98ed3cbee1a745cd8f (patch) | |
| tree | 59c594e41320db3a58677857f30c21688427981d /kernel | |
| parent | 1d88f1cf9f2088de7825f5292db5b40d4f73d036 (diff) | |
| download | yosys-361e0d62ffd90b87c94bfc98ed3cbee1a745cd8f.tar.gz yosys-361e0d62ffd90b87c94bfc98ed3cbee1a745cd8f.tar.bz2 yosys-361e0d62ffd90b87c94bfc98ed3cbee1a745cd8f.zip | |
Replaced depricated NEW_WIRE macro with module->addWire() calls
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 3c6c97242..9b3e44179 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -141,9 +141,6 @@ namespace RTLIL #define NEW_ID \ RTLIL::new_id(__FILE__, __LINE__, __FUNCTION__) -#define NEW_WIRE(_mod, _width) \ - (_mod)->addWire(NEW_ID, _width) - template <typename T> struct sort_by_name { bool operator()(T *a, T *b) const { return a->name < b->name; |