| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | Update copyright header | Clifford Wolf | 2018-03-04 | 1 | -1/+1 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add $allconst and $allseq cell types | Clifford Wolf | 2018-02-23 | 3 | -1/+25 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Do not create deep backtraces unless in ENABLE_DEBUG mode | Clifford Wolf | 2018-02-03 | 1 | -0/+4 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add support for "yosys -E" | Clifford Wolf | 2018-01-07 | 4 | -2/+36 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Bugfix in hierarchy handling of blackbox module ports | Clifford Wolf | 2018-01-05 | 2 | -2/+4 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add RTLIL::Const::is_fully_ones() | Clifford Wolf | 2017-12-14 | 2 | -0/+12 | |
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| * | Add SigSpec::is_fully_ones() | Clifford Wolf | 2017-12-14 | 2 | -0/+16 | |
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| * | Use quote includes for yosys.h | Kevin Kiningham | 2017-12-13 | 2 | -2/+2 | |
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| * | Add support for editline as replacement for readline | Clifford Wolf | 2017-11-08 | 2 | -10/+29 | |
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| * | Add src arguments to all cell creator helper functions | Clifford Wolf | 2017-09-09 | 2 | -209/+244 | |
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| * | Update more stuff to use get_src_attribute() and set_src_attribute() | Clifford Wolf | 2017-09-01 | 1 | -1/+1 | |
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| * | Merge remote-tracking branch 'upstream/master' | Jason Lowdermilk | 2017-08-30 | 2 | -0/+20 | |
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| | * | Add {get,set}_src_attribute() methods on RTLIL::AttrObject | Clifford Wolf | 2017-08-30 | 2 | -0/+20 | |
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| * | | fix indent level | Jason Lowdermilk | 2017-08-30 | 1 | -2/+2 | |
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| * | | Add support for source line tracking through synthesis phase | Jason Lowdermilk | 2017-08-29 | 2 | -21/+22 | |
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| * | Add hashlib support for hashing of pools | Clifford Wolf | 2017-08-22 | 1 | -0/+7 | |
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| * | Add consteval support for $_ANDNOT_ and $_ORNOT_ | Clifford Wolf | 2017-08-22 | 1 | -0/+4 | |
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| * | Add Const methods is_fully_zero(), is_fully_def(), and is_fully_undef() | Clifford Wolf | 2017-08-18 | 2 | -0/+37 | |
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| * | Auto-detect JSON front-end | Clifford Wolf | 2017-08-09 | 1 | -0/+2 | |
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| * | Add log_warning_noprefix() API, Use for Verific warnings and errors | Clifford Wolf | 2017-07-27 | 2 | -0/+36 | |
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| * | Add "using std::get" to yosys.h | Clifford Wolf | 2017-07-25 | 1 | -0/+1 | |
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| * | Change intptr_t to uintptr_t in hashlib.h | Clifford Wolf | 2017-07-18 | 1 | -1/+1 | |
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| * | Fix build warnings for win64 | Robert Ou | 2017-07-17 | 1 | -1/+1 | |
| | | | | | Win64 has a 32-bit long. Use intptr_t to work on any data model. | |||||
| * | Fix history namespace collision | Clifford Wolf | 2017-06-20 | 1 | -10/+10 | |
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| * | Store command history when terminating with an error | Clifford Wolf | 2017-06-20 | 3 | -17/+31 | |
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| * | Add "setundef -anyseq" | Clifford Wolf | 2017-05-28 | 1 | -12/+12 | |
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| * | Enable readline and tcl in mxe builds | Clifford Wolf | 2017-05-17 | 1 | -0/+10 | |
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| * | Add missing AndnotGate() and OrnotGate() declarations to rtlil.h | Clifford Wolf | 2017-05-17 | 1 | -13/+15 | |
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| * | Add $_ANDNOT_ and $_ORNOT_ gates | Clifford Wolf | 2017-05-17 | 6 | -55/+94 | |
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| * | Add ConstEval defaultval feature | Clifford Wolf | 2017-04-05 | 1 | -1/+8 | |
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| * | Add front-end detection for *.tcl files | Clifford Wolf | 2017-03-28 | 1 | -1/+6 | |
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| * | Add $live and $fair cell types, add support for s_eventually keyword | Clifford Wolf | 2017-02-25 | 3 | -1/+21 | |
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| * | Fix mingw compile issue (2nd attempt) | Clifford Wolf | 2017-02-23 | 1 | -2/+2 | |
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| * | Fix mingw compile issue (maybe.. I can't test it) | Clifford Wolf | 2017-02-23 | 1 | -2/+2 | |
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| * | Fix eval implementation of $_NOR_ | Clifford Wolf | 2017-02-16 | 1 | -1/+1 | |
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| * | Add "yosys -w" for suppressing warnings | Clifford Wolf | 2017-02-12 | 3 | -11/+34 | |
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| * | Add log_wire() API | Clifford Wolf | 2017-02-11 | 2 | -0/+8 | |
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| * | Fix undef propagation bug in $pmux SAT model | Clifford Wolf | 2017-02-05 | 1 | -14/+4 | |
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| * | Add $cover cell type and SVA cover() support | Clifford Wolf | 2017-02-04 | 3 | -1/+11 | |
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| * | Fix RTLIL::Memory::start_offset initialization | Clifford Wolf | 2017-01-25 | 1 | -0/+1 | |
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| * | Bugfix in RTLIL::SigSpec::remove2() | Clifford Wolf | 2016-12-31 | 1 | -3/+4 | |
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| * | Simplified log_spacer() code | Clifford Wolf | 2016-12-23 | 1 | -6/+2 | |
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| * | Added "yosys -W regex" | Clifford Wolf | 2016-12-22 | 3 | -2/+44 | |
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| * | Added AIGER back-end to automatic back-end detection | Clifford Wolf | 2016-12-21 | 1 | -0/+2 | |
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| * | Bugfix in comment handling | Clifford Wolf | 2016-12-13 | 1 | -1/+1 | |
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| * | Remember global declarations and defines accross read_verilog calls | Clifford Wolf | 2016-11-15 | 2 | -1/+4 | |
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| * | Some minor build fixes for Visual C | Clifford Wolf | 2016-10-14 | 2 | -1/+5 | |
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| * | Added $anyseq cell type | Clifford Wolf | 2016-10-14 | 4 | -3/+19 | |
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| * | Added $global_clock verilog syntax support for creating $ff cells | Clifford Wolf | 2016-10-14 | 1 | -1/+2 | |
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| * | Added $ff and $_FF_ cell types | Clifford Wolf | 2016-10-12 | 4 | -1/+31 | |
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index : iCE40/yosys | |
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