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* Improved checking of internal cell conventionsClifford Wolf2014-02-081-8/+17
* Added $slice and $concat to CellTypes listClifford Wolf2014-02-071-0/+2
* Added $slice and $concat cell typesClifford Wolf2014-02-073-4/+54
* Stronger checking of internal cellsClifford Wolf2014-02-071-29/+37
* Added echo commandClifford Wolf2014-02-073-4/+47
* Added generic RTLIL::SigSpec::parse_sel() with support for selection variablesClifford Wolf2014-02-062-0/+19
* Added support for #-comments in same line as commandClifford Wolf2014-02-061-0/+2
* Added support for backslash continuation in script filesClifford Wolf2014-02-061-2/+13
* Fixed bug in sequential sat proofs and improved handling of assertsClifford Wolf2014-02-041-7/+16
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-031-0/+2
* Added RTLIL::SigSpec::to_single_sigbit()Clifford Wolf2014-02-022-0/+10
* Added yosys -H for command listClifford Wolf2014-01-301-1/+7
* Added -h command line optionClifford Wolf2014-01-291-2/+8
* Added $assert support to satgenClifford Wolf2014-01-191-0/+21
* Added $assert cellClifford Wolf2014-01-192-0/+8
* Some improvements in log_dump_val_worker() templatesClifford Wolf2014-01-171-1/+6
* Added select -assert-none and -assert-anyClifford Wolf2014-01-171-0/+3
* Fixed SAT and ConstEval undef handling for $pmux and $safe_pmuxClifford Wolf2014-01-032-10/+43
* Added RTLIL::SigSpec::optimized() APIClifford Wolf2014-01-032-0/+8
* Added correct handling of $memwr priorityClifford Wolf2014-01-031-0/+1
* Added SAT undef model for $pmux and $safe_pmuxClifford Wolf2014-01-021-4/+19
* Major rewrite of "freduce" commandClifford Wolf2014-01-021-5/+3
* Added additional checks for A_SIGNED == B_SIGNED for cells with that constraintClifford Wolf2013-12-311-4/+11
* Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen)Clifford Wolf2013-12-291-11/+8
* Added $bu0 cell (for easy correct $eq/$ne mapping)Clifford Wolf2013-12-284-1/+12
* Fixed sat handling of $eqx and $nex with unequal port widthsClifford Wolf2013-12-271-0/+2
* Small cleanup in SatGenClifford Wolf2013-12-271-2/+0
* Fixed sat handling of $eqx and $nex cellsClifford Wolf2013-12-271-1/+12
* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-273-5/+21
* Added proper === and !== support in constant expressionsClifford Wolf2013-12-272-0/+31
* Added log_dump() APIClifford Wolf2013-12-201-0/+54
* Added "sat" undef support and "sat -set-init" optionsClifford Wolf2013-12-071-13/+24
* Fixed uninitialized const flags bugClifford Wolf2013-12-071-1/+1
* Fixes and improvements in RTLIL::SigSpec::parseClifford Wolf2013-12-071-2/+12
* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-042-4/+3
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-042-7/+39
* Added Pass:call_newsel APIClifford Wolf2013-12-022-0/+27
* Added "history" commandClifford Wolf2013-12-021-0/+18
* Using RTLIL::id2cstr for prompt printingClifford Wolf2013-11-291-1/+1
* Improvements in satgen undef handlingClifford Wolf2013-11-251-73/+170
* Improvements in satgen undef handlingClifford Wolf2013-11-251-27/+122
* Started implementing undef handling in satgenClifford Wolf2013-11-251-25/+172
* Added module->avail_parameters (for advanced techmap features)Clifford Wolf2013-11-241-0/+1
* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-242-8/+1
* Implemented correct handling of signed module parametersClifford Wolf2013-11-242-2/+3
* Added more generic _TECHMAP_ wire mechanism to techmap passClifford Wolf2013-11-231-0/+6
* Some driver changes/fixesClifford Wolf2013-11-221-5/+5
* Added more performance measurement infrastructureClifford Wolf2013-11-221-0/+41
* Massive performance improvement from refactoring RTLIL::SigSpec::optimize()Clifford Wolf2013-11-221-30/+13
* Added SigBit struct and refactored RTLIL::SigSpec::extractClifford Wolf2013-11-222-24/+119