| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | sim/formalff: Clock handling for yw cosim | Jannis Harder | 2023-01-11 | 1 | -2/+2 |
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| * | sim: Improvements and fixes for yw cosim | Jannis Harder | 2023-01-11 | 1 | -0/+12 |
| | | | | | | | * Fixed $cover handling * Improved sparse memory handling when writing traces * JSON summary output | ||||
| * | New kernel/yw.{h,cc} to support reading Yosys witness files | Jannis Harder | 2023-01-11 | 1 | -0/+170 |
| This contains parsing code as well as generic routines to associate the hierarchical signals paths within a Yosys witness file to a loaded RTLIL design, including support for memories. | |||||
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index : iCE40/yosys | |
| [no description] |
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