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* Fixed a few VS warningsClifford Wolf2014-10-171-1/+1
* Added format __attribute__ to stringf()Clifford Wolf2014-10-101-1/+1
* Renamed TRUE/FALSE to CONST_TRUE/CONST_FALSE because of name collision on Win32Clifford Wolf2014-10-101-52/+52
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-101-32/+32
* satgen import sigbit apiClifford Wolf2014-10-031-1/+17
* namespace YosysClifford Wolf2014-09-271-0/+5
* Simplified $fa undef modelClifford Wolf2014-09-081-14/+1
* Added $lcu cell typeClifford Wolf2014-09-081-0/+32
* Added "$fa" cell typeClifford Wolf2014-09-081-0/+49
* Added $macc SAT modelClifford Wolf2014-09-061-0/+71
* Removed $bu0 cell typeClifford Wolf2014-09-041-3/+3
* Using $pos models for $bu0Clifford Wolf2014-09-031-1/+1
* Fixes in $alu SAT- and eval-modelsClifford Wolf2014-09-031-4/+3
* Small bug fixes in $not, $neg, and $shiftx modelsClifford Wolf2014-09-021-3/+4
* Added SAT model for $alu cellsClifford Wolf2014-09-011-2/+69
* Added $lut support in test_cell, techmap, satgenClifford Wolf2014-08-311-1/+50
* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...Clifford Wolf2014-08-161-7/+81
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-151-1/+1
* RIP $safe_pmuxClifford Wolf2014-08-141-9/+1
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-85/+85
* Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT modelsClifford Wolf2014-07-301-36/+39
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-291-4/+14
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-4/+4
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-85/+85
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-85/+85
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-231-6/+4
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-7/+7
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-7/+7
* Bugfix in satgen for cells with wider in- than outputs.Clifford Wolf2014-07-211-1/+9
* Added libs/minisat (copy of minisat git master)Clifford Wolf2014-03-121-6/+1
* Fixed use of frozen literals in SatGenClifford Wolf2014-03-061-3/+2
* Strictly zero-extend unsigned A-inputs of shift operationsClifford Wolf2014-03-061-1/+1
* Added support for $bu0 to SatGenClifford Wolf2014-02-261-4/+4
* Added support for Minisat::SimpSolver + ezSAT frezze() APIClifford Wolf2014-02-231-0/+1
* Added $slice and $concat cell typesClifford Wolf2014-02-071-0/+21
* Fixed bug in sequential sat proofs and improved handling of assertsClifford Wolf2014-02-041-7/+16
* Added $assert support to satgenClifford Wolf2014-01-191-0/+21
* Fixed SAT and ConstEval undef handling for $pmux and $safe_pmuxClifford Wolf2014-01-031-6/+37
* Added SAT undef model for $pmux and $safe_pmuxClifford Wolf2014-01-021-4/+19
* Major rewrite of "freduce" commandClifford Wolf2014-01-021-5/+3
* Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen)Clifford Wolf2013-12-291-11/+8
* Fixed sat handling of $eqx and $nex with unequal port widthsClifford Wolf2013-12-271-0/+2
* Small cleanup in SatGenClifford Wolf2013-12-271-2/+0
* Fixed sat handling of $eqx and $nex cellsClifford Wolf2013-12-271-1/+12
* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-271-4/+16
* Added "sat" undef support and "sat -set-init" optionsClifford Wolf2013-12-071-13/+24
* Improvements in satgen undef handlingClifford Wolf2013-11-251-73/+170
* Improvements in satgen undef handlingClifford Wolf2013-11-251-27/+122
* Started implementing undef handling in satgenClifford Wolf2013-11-251-25/+172
* Added verification of SAT model to "eval -vloghammer_report" commandClifford Wolf2013-11-091-6/+5
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