iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fixed memory corruption related to id2cstr()	Clifford Wolf	2014-08-02	1	-2/+2
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-62/+35
*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02	1	-9/+47
*	Added ModIndex helper class, some changes to RTLIL::Monitor	Clifford Wolf	2014-08-01	1	-5/+5
*	Packed SigBit::data and SigBit::offset in a union	Clifford Wolf	2014-08-01	1	-9/+11
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-4/+11
*	Added RTLIL::Monitor	Clifford Wolf	2014-07-31	1	-2/+18
*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31	1	-0/+20
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	1	-14/+4
*	Added techmap CONSTMAP feature	Clifford Wolf	2014-07-30	1	-0/+3
*	Added "kernel/yosys.h" and "kernel/yosys.cc"	Clifford Wolf	2014-07-30	1	-12/+2
*	Added "techmap -map %{design-name}"	Clifford Wolf	2014-07-29	1	-0/+5
*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	1	-8/+14
*	Added wire->upto flag for signals such as "wire [0:7] x;"	Clifford Wolf	2014-07-28	1	-1/+1
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-8/+8
*	Added std::initializer_list<> constructor to SigSpec	Clifford Wolf	2014-07-28	1	-0/+3
*	Added proper Design->addModule interface	Clifford Wolf	2014-07-27	1	-1/+6
*	Added RTLIL::SigSpecConstIterator	Clifford Wolf	2014-07-27	1	-0/+18
*	Added RTLIL::Module::wire(id) and cell(id) lookup functions	Clifford Wolf	2014-07-27	1	-2/+8
*	Added RTLIL::Design::modules()	Clifford Wolf	2014-07-27	1	-0/+3
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
*	Added conversion from ObjRange to std::vector and std::set	Clifford Wolf	2014-07-27	1	-0/+15
*	Added RTLIL::ObjIterator and RTLIL::ObjRange	Clifford Wolf	2014-07-27	1	-1/+88
*	Using std::move() in SigSpec move constructor	Clifford Wolf	2014-07-27	1	-4/+4
*	Added RTLIL::SigSpec move constructor and move assignment operator	Clifford Wolf	2014-07-27	1	-0/+15
*	Mostly cosmetic changes to rtlil.h	Clifford Wolf	2014-07-27	1	-17/+57
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-2/+2
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-1/+1
*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-6/+10
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-0/+3
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26	1	-0/+1
*	Added some missing "const" in rtlil.h	Clifford Wolf	2014-07-26	1	-4/+4
*	Added RTLIL::Module::connections()	Clifford Wolf	2014-07-26	1	-0/+1
*	Added RTLIL::Module::connect(const RTLIL::SigSig&)	Clifford Wolf	2014-07-26	1	-0/+1
*	Automatically pack SigSpec on copy/assign	Clifford Wolf	2014-07-26	1	-0/+3
*	Added new RTLIL::Cell port access methods	Clifford Wolf	2014-07-26	1	-0/+8
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-10/+26
*	Added copy-constructor-like module->addCell(name, other) method	Clifford Wolf	2014-07-26	1	-0/+1
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-2/+19
*	Added RTLIL::SigSpec is_chunk()/as_chunk() API	Clifford Wolf	2014-07-25	1	-0/+3
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	1	-1/+3
*	Small changes regarding cover() and check() in SigSpec	Clifford Wolf	2014-07-24	1	-0/+4
*	Added hashing to RTLIL::SigSpec relational and equal operators	Clifford Wolf	2014-07-23	1	-2/+7
*	Added RTLIL::SigSpec::repeat()	Clifford Wolf	2014-07-23	1	-0/+2
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-7/+0
*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23	1	-3/+0
*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23	1	-2/+2
*	Replaced RTLIL::SigSpec::operator!=() with inline version	Clifford Wolf	2014-07-23	1	-1/+1
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-6/+2
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3	Clifford Wolf	2014-07-23	1	-2/+8