| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Added RTLIL::SigSpec::to_sigbit_map() | Clifford Wolf | 2014-08-14 | 1 | -0/+16 |
| * | Added sig.{replace,remove,extract} variants for std::{map,set} pattern | Clifford Wolf | 2014-08-14 | 1 | -24/+53 |
| * | Added module->ports | Clifford Wolf | 2014-08-14 | 1 | -1/+9 |
| * | Refactoring of CellType class | Clifford Wolf | 2014-08-14 | 1 | -10/+6 |
| * | RIP $safe_pmux | Clifford Wolf | 2014-08-14 | 1 | -4/+3 |
| * | Added support for truncating of wires to wreduce pass | Clifford Wolf | 2014-08-05 | 1 | -0/+30 |
| * | Bugfix in "techmap -extern" | Clifford Wolf | 2014-08-02 | 1 | -10/+16 |
| * | Removed at() method from RTLIL::IdString | Clifford Wolf | 2014-08-02 | 1 | -2/+2 |
| * | No implicit conversion from IdString to anything else | Clifford Wolf | 2014-08-02 | 1 | -14/+14 |
| * | Improvements in new RTLIL::IdString implementation | Clifford Wolf | 2014-08-02 | 1 | -2/+2 |
| * | Implemented new reference counting RTLIL::IdString | Clifford Wolf | 2014-08-02 | 1 | -2/+6 |
| * | More cleanups related to RTLIL::IdString usage | Clifford Wolf | 2014-08-02 | 1 | -1/+1 |
| * | Added ModIndex helper class, some changes to RTLIL::Monitor | Clifford Wolf | 2014-08-01 | 1 | -13/+23 |
| * | Packed SigBit::data and SigBit::offset in a union | Clifford Wolf | 2014-08-01 | 1 | -1/+3 |
| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -82/+102 |
| * | Added RTLIL::Monitor | Clifford Wolf | 2014-07-31 | 1 | -94/+79 |
| * | Added module->design and cell->module, wire->module pointers | Clifford Wolf | 2014-07-31 | 1 | -0/+83 |
| * | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 | 1 | -4/+4 |
| * | Added "techmap -map %{design-name}" | Clifford Wolf | 2014-07-29 | 1 | -0/+5 |
| * | Added $shift and $shiftx cell types (needed for correct part select behavior) | Clifford Wolf | 2014-07-29 | 1 | -1/+4 |
| * | Added wire->upto flag for signals such as "wire [0:7] x;" | Clifford Wolf | 2014-07-28 | 1 | -0/+2 |
| * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 1 | -60/+59 |
| * | Added std::initializer_list<> constructor to SigSpec | Clifford Wolf | 2014-07-28 | 1 | -0/+12 |
| * | Added cover() to all SigSpec constructors | Clifford Wolf | 2014-07-28 | 1 | -0/+22 |
| * | Added proper Design->addModule interface | Clifford Wolf | 2014-07-27 | 1 | -3/+36 |
| * | Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs | Clifford Wolf | 2014-07-27 | 1 | -9/+26 |
| * | Added RTLIL::Module::wire(id) and cell(id) lookup functions | Clifford Wolf | 2014-07-27 | 1 | -0/+12 |
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -9/+9 |
| * | Added RTLIL::ObjIterator and RTLIL::ObjRange | Clifford Wolf | 2014-07-27 | 1 | -6/+23 |
| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -12/+12 |
| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -20/+20 |
| * | Changed more code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 1 | -1/+13 |
| * | Changed a lot of code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 1 | -0/+40 |
| * | Added RTLIL::Cell::has(portname) | Clifford Wolf | 2014-07-26 | 1 | -4/+9 |
| * | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 1 | -11/+11 |
| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -82/+82 |
| * | Added some missing "const" in rtlil.h | Clifford Wolf | 2014-07-26 | 1 | -5/+5 |
| * | Added RTLIL::Module::connections() | Clifford Wolf | 2014-07-26 | 1 | -0/+5 |
| * | Added RTLIL::Module::connect(const RTLIL::SigSig&) | Clifford Wolf | 2014-07-26 | 1 | -0/+5 |
| * | Automatically pack SigSpec on copy/assign | Clifford Wolf | 2014-07-26 | 1 | -17/+60 |
| * | Added new RTLIL::Cell port access methods | Clifford Wolf | 2014-07-26 | 1 | -0/+63 |
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -83/+88 |
| * | Added copy-constructor-like module->addCell(name, other) method | Clifford Wolf | 2014-07-26 | 1 | -8/+11 |
| * | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 1 | -2/+35 |
| * | Added RTLIL::SigSpec is_chunk()/as_chunk() API | Clifford Wolf | 2014-07-25 | 1 | -0/+17 |
| * | Fixed typo in cover id | Clifford Wolf | 2014-07-25 | 1 | -1/+1 |
| * | Replaced more old SigChunk programming patterns | Clifford Wolf | 2014-07-24 | 1 | -0/+17 |
| * | Some improvements in SigSpec packing/unpacking and checking | Clifford Wolf | 2014-07-24 | 1 | -8/+29 |
| * | Small changes regarding cover() and check() in SigSpec | Clifford Wolf | 2014-07-24 | 1 | -10/+5 |
| * | Added support for YOSYS_COVER_FILE env variable | Clifford Wolf | 2014-07-24 | 1 | -0/+2 |
