| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 1 | -11/+11 |
| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -82/+82 |
| * | Added some missing "const" in rtlil.h | Clifford Wolf | 2014-07-26 | 1 | -5/+5 |
| * | Added RTLIL::Module::connections() | Clifford Wolf | 2014-07-26 | 1 | -0/+5 |
| * | Added RTLIL::Module::connect(const RTLIL::SigSig&) | Clifford Wolf | 2014-07-26 | 1 | -0/+5 |
| * | Automatically pack SigSpec on copy/assign | Clifford Wolf | 2014-07-26 | 1 | -17/+60 |
| * | Added new RTLIL::Cell port access methods | Clifford Wolf | 2014-07-26 | 1 | -0/+63 |
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -83/+88 |
| * | Added copy-constructor-like module->addCell(name, other) method | Clifford Wolf | 2014-07-26 | 1 | -8/+11 |
| * | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 1 | -2/+35 |
| * | Added RTLIL::SigSpec is_chunk()/as_chunk() API | Clifford Wolf | 2014-07-25 | 1 | -0/+17 |
| * | Fixed typo in cover id | Clifford Wolf | 2014-07-25 | 1 | -1/+1 |
| * | Replaced more old SigChunk programming patterns | Clifford Wolf | 2014-07-24 | 1 | -0/+17 |
| * | Some improvements in SigSpec packing/unpacking and checking | Clifford Wolf | 2014-07-24 | 1 | -8/+29 |
| * | Small changes regarding cover() and check() in SigSpec | Clifford Wolf | 2014-07-24 | 1 | -10/+5 |
| * | Added support for YOSYS_COVER_FILE env variable | Clifford Wolf | 2014-07-24 | 1 | -0/+2 |
| * | Added cover() calls to RTLIL::SigSpec methods | Clifford Wolf | 2014-07-24 | 1 | -5/+93 |
| * | Added hashing to RTLIL::SigSpec relational and equal operators | Clifford Wolf | 2014-07-23 | 1 | -15/+64 |
| * | Disabled RTLIL::SigSpec::check() in release builds | Clifford Wolf | 2014-07-23 | 1 | -0/+2 |
| * | Fixed release build | Clifford Wolf | 2014-07-23 | 1 | -0/+2 |
| * | Added RTLIL::SigSpec::repeat() | Clifford Wolf | 2014-07-23 | 1 | -0/+8 |
| * | Removed RTLIL::SigSpec::optimize() | Clifford Wolf | 2014-07-23 | 1 | -105/+9 |
| * | Turned RTLIL::SigSpec::optimize() to a no-op: a packed SigSpec is now always ... | Clifford Wolf | 2014-07-23 | 1 | -7/+42 |
| * | Removed RTLIL::SigSpec::expand() method | Clifford Wolf | 2014-07-23 | 1 | -41/+0 |
| * | Replaced RTLIL::SigSpec::operator!=() with inline version | Clifford Wolf | 2014-07-23 | 1 | -7/+0 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 | Clifford Wolf | 2014-07-23 | 1 | -14/+10 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 | Clifford Wolf | 2014-07-23 | 1 | -16/+2 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3 | Clifford Wolf | 2014-07-23 | 1 | -0/+32 |
| * | Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&) | Clifford Wolf | 2014-07-23 | 1 | -4/+4 |
| * | SigSpec refactoring: More cleanups of old SigSpec use pattern | Clifford Wolf | 2014-07-22 | 1 | -1/+11 |
| * | SigSpec refactoring: rewrote some RTLIL::SigSpec methods to use unpacked form | Clifford Wolf | 2014-07-22 | 1 | -182/+113 |
| * | Removed RTLIL::SigChunk::compare() | Clifford Wolf | 2014-07-22 | 1 | -24/+5 |
| * | SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack api | Clifford Wolf | 2014-07-22 | 1 | -8/+103 |
| * | SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created... | Clifford Wolf | 2014-07-22 | 1 | -1/+1 |
| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -44/+44 |
| * | SigSpec refactoring: renamed the SigSpec members to chunks_ and width_ and ad... | Clifford Wolf | 2014-07-22 | 1 | -149/+149 |
| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -193/+193 |
| * | Removed deprecated module->new_wire() | Clifford Wolf | 2014-07-21 | 1 | -15/+6 |
| * | Added module->remove(), module->addWire(), module->addCell(), cell->check() | Clifford Wolf | 2014-07-21 | 1 | -8/+39 |
| * | Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion | Clifford Wolf | 2014-07-20 | 1 | -3/+10 |
| * | Added function-like cell creation helpers | Clifford Wolf | 2014-07-18 | 1 | -73/+103 |
| * | Fixed RTLIL::SigSpec::append_bit() for appending constants | Clifford Wolf | 2014-07-17 | 1 | -2/+3 |
| * | Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal | Clifford Wolf | 2014-07-16 | 1 | -2/+2 |
| * | Add support for cell arrays | Clifford Wolf | 2014-06-07 | 1 | -1/+2 |
| * | Added support for dlatchsr cells | Clifford Wolf | 2014-03-31 | 1 | -1/+58 |
| * | Fixed typo in RTLIL::Module::addAdff() | Clifford Wolf | 2014-03-17 | 1 | -1/+1 |
| * | Fixed typo in RTLIL::Module::{addSshl,addSshr} | Clifford Wolf | 2014-03-15 | 1 | -2/+2 |
| * | Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() API | Clifford Wolf | 2014-03-15 | 1 | -1/+54 |
| * | Progress in Verific bindings | Clifford Wolf | 2014-03-14 | 1 | -1/+1 |
| * | Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate API | Clifford Wolf | 2014-03-14 | 1 | -0/+42 |
