| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Start restoring memory state from VCD/FST | Miodrag Milanovic | 2022-05-04 | 1 | -0/+2 |
| * | Proper scope naming from FST | Miodrag Milanovic | 2022-03-30 | 1 | -1/+0 |
| * | Recognize registers and set initial state for them in tb | Miodrag Milanovic | 2022-03-16 | 1 | -0/+1 |
| * | VCD reader support by using external tool | Miodrag Milanovic | 2022-02-28 | 1 | -0/+1 |
| * | Add support for various ff/latch cells simulation | Miodrag Milanovic | 2022-02-16 | 1 | -11/+11 |
| * | Display simulation time data | Miodrag Milanovic | 2022-01-31 | 1 | -0/+2 |
| * | cleanup | Miodrag Milanovic | 2022-01-28 | 1 | -1/+0 |
| * | Do actual compare | Miodrag Milanovic | 2022-01-28 | 1 | -7/+6 |
| * | Add more options and time handling | Miodrag Milanovic | 2022-01-28 | 1 | -0/+2 |
| * | Fix tabs/spaces | Miodrag Milanovic | 2022-01-26 | 1 | -31/+31 |
| * | Add fstdata helper class | Miodrag Milanovic | 2022-01-26 | 1 | -0/+79 |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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