iCE40/yosys - clone of https://github.com/YosysHQ/yosys

	Commit message (Expand)	Author	Age	Files	Lines
*	Observe $TMPDIR variable when creating tmp files	Mohamed A. Bamakhrama	2022-05-27	1	-1/+1
*	Handle possible non-memory indexed data	Miodrag Milanovic	2022-05-06	1	-8/+10
*	map memory location to wire value, if memory is converted to FFs	Miodrag Milanovic	2022-05-04	1	-0/+4
*	Start restoring memory state from VCD/FST	Miodrag Milanovic	2022-05-04	1	-1/+31
*	Ignore change on last edge	Miodrag Milanovic	2022-04-22	1	-4/+5
*	Proper scope naming from FST	Miodrag Milanovic	2022-03-30	1	-8/+4
*	More verbose warnings	Miodrag Milanovic	2022-03-18	1	-1/+2
*	Recognize registers and set initial state for them in tb	Miodrag Milanovic	2022-03-16	1	-0/+1
*	VCD reader support by using external tool	Miodrag Milanovic	2022-02-28	1	-0/+19
*	Fix for last clock edge data	Miodrag Milanovic	2022-02-25	1	-0/+1
*	Changed error message	Miodrag Milanovic	2022-02-18	1	-1/+1
*	Add support for various ff/latch cells simulation	Miodrag Milanovic	2022-02-16	1	-98/+43
*	Error detection for co-simulation	Miodrag Milanovic	2022-02-04	1	-0/+2
*	bug fix and cleanups	Miodrag Milanovic	2022-02-04	1	-1/+1
*	Cleanup	Miodrag Milanovic	2022-01-31	1	-1/+0
*	Display simulation time data	Miodrag Milanovic	2022-01-31	1	-1/+21
*	ignore not found private signals	Miodrag Milanovic	2022-01-28	1	-2/+1
*	preserve VCD mangled names	Miodrag Milanovic	2022-01-28	1	-1/+3
*	detect edges even when x	Miodrag Milanovic	2022-01-28	1	-2/+2
*	cleanup	Miodrag Milanovic	2022-01-28	1	-13/+1
*	Do actual compare	Miodrag Milanovic	2022-01-28	1	-65/+41
*	Add more options and time handling	Miodrag Milanovic	2022-01-28	1	-0/+1
*	Add fstdata helper class	Miodrag Milanovic	2022-01-26	1	-0/+265