iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-1/+1
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-7/+7
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-4/+4
*	Added support for dlatchsr cells	Clifford Wolf	2014-03-31	1	-0/+9
*	Fixed const folding of $bu0 cells	Clifford Wolf	2014-02-27	1	-1/+1
*	Added $slice and $concat to CellTypes list	Clifford Wolf	2014-02-07	1	-0/+2
*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07	1	-4/+15
*	Added $assert cell	Clifford Wolf	2014-01-19	1	-0/+1
*	Added $bu0 cell (for easy correct $eq/$ne mapping)	Clifford Wolf	2013-12-28	1	-0/+2
*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27	1	-0/+4
*	Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_	Clifford Wolf	2013-10-18	1	-0/+14
*	Added $sr, $dffsr and $dlatch cell types	Clifford Wolf	2013-10-18	1	-1/+3
*	Added $lut cells and abc lut mapping support	Clifford Wolf	2013-07-23	1	-0/+3
*	Fixed even more ConstEval bugs found using xsthammer	Clifford Wolf	2013-06-14	1	-2/+5
*	Added consteval testing to xsthammer and fixed bugs	Clifford Wolf	2013-06-13	1	-0/+8
*	Added log_assert() api	Clifford Wolf	2013-05-24	1	-2/+4
*	Added additional functionality and cleanups in sigtools.h and celltypes.h	Clifford Wolf	2013-03-15	1	-0/+9
*	Added #ci and #co selection operators	Clifford Wolf	2013-03-14	1	-5/+15
*	Added $sr cell type to celltypes.h	Clifford Wolf	2013-03-14	1	-0/+1
*	Added library support to celltypes class and show pass	Clifford Wolf	2013-03-03	1	-4/+35
*	initial import	Clifford Wolf	2013-01-05	1	-0/+210