iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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\| *	Merge pull request #848 from YosysHQ/clifford/fix763	Clifford Wolf	2019-03-02	1	-1/+5
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\| \| *	Fix error for wire decl in always block, fixes #763	Clifford Wolf	2019-03-02	1	-1/+5
\| * \|	Only run derive on blackbox modules when ports have dynamic size	Clifford Wolf	2019-03-02	2	-0/+20
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\| *	Fix $global_clock handling vs autowire	Clifford Wolf	2019-03-02	1	-1/+1
\| *	Fix $readmem[hb] for mem2reg memories, fixes #785	Clifford Wolf	2019-03-02	1	-0/+35
\| *	Use mem2reg on memories that only have constant-index write ports	Clifford Wolf	2019-03-01	2	-0/+13
\| *	Improve "read" error msg	Clifford Wolf	2019-02-28	1	-1/+1
\| *	Fix handling of defparam for when default_nettype is none	Clifford Wolf	2019-02-24	1	-0/+4
\| *	Check if Verific was built with DB_PRESERVE_INITIAL_VALUE	Clifford Wolf	2019-02-24	1	-0/+4
\| *	Fixes related to handling of autowires and upto-ranges, fixes #814	Clifford Wolf	2019-02-21	2	-9/+12
\| *	Fix handling of expression width in $past, fixes #810	Clifford Wolf	2019-02-21	1	-1/+1
\| *	Fix segfault in printing of some internal error messages	Clifford Wolf	2019-02-21	1	-2/+2
* \|	Add author name	Eddie Hung	2019-03-19	1	-0/+1
* \|	Fix for using POSIX basename	Eddie Hung	2019-02-19	1	-2/+4
* \|	Missing OSX headers?	Eddie Hung	2019-02-17	1	-0/+5
* \|	read_aiger to ignore line after ands for ascii, not binary	Eddie Hung	2019-02-17	1	-2/+1
* \|	Merge https://github.com/YosysHQ/yosys into read_aiger	Eddie Hung	2019-02-17	1	-5/+4
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\| *	Fix sign handling of real constants	Clifford Wolf	2019-02-13	1	-5/+4
* \|	Merge branch 'read_aiger' of github.com:eddiehung/yosys into read_aiger	Eddie Hung	2019-02-12	1	-3/+1
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\| * \|	Do not break for constraints	Eddie Hung	2019-02-11	1	-1/+0
\| * \|	No increment line_count for binary ANDs	Eddie Hung	2019-02-11	1	-1/+1
\| * \|	Do not ignore newline after AND in binary AIG	Eddie Hung	2019-02-11	1	-1/+0
* \| \|	Use module->add{Not,And}Gate() functions	Eddie Hung	2019-02-12	1	-8/+2
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* \|	addDff -> addDffGate as per @daveshah1	Eddie Hung	2019-02-08	1	-1/+1
* \|	Fix tabulation	Eddie Hung	2019-02-08	1	-28/+28
* \|	-module_name arg to go before -clk_name	Eddie Hung	2019-02-08	1	-7/+7
* \|	Add missing "[options]" to read_blif help	Eddie Hung	2019-02-08	1	-1/+1
* \|	Allow module name to be determined by argument too	Eddie Hung	2019-02-08	2	-14/+44
* \|	Refactor into AigerReader class	Eddie Hung	2019-02-08	2	-79/+92
* \|	Parse binary AIG files	Eddie Hung	2019-02-08	1	-49/+164
* \|	Refactor to parse_aiger_header()	Eddie Hung	2019-02-08	1	-26/+32
* \|	Add comment	Eddie Hung	2019-02-08	1	-0/+1
* \|	Handle reset logic in latches	Eddie Hung	2019-02-08	1	-2/+17
* \|	Change literal vars from int to unsigned	Eddie Hung	2019-02-08	1	-1/+1
* \|	Create clk outside of latch loop	Eddie Hung	2019-02-08	1	-7/+9
* \|	Handle latch symbols too	Eddie Hung	2019-02-08	1	-3/+1
* \|	Remove return after log_error	Eddie Hung	2019-02-08	1	-27/+9
* \|	Add support for symbol tables	Eddie Hung	2019-02-08	1	-1/+49
* \|	Stub for binary AIGER	Eddie Hung	2019-02-08	1	-3/+8
* \|	Refactor	Eddie Hung	2019-02-06	1	-1/+8
* \|	WIP	Eddie Hung	2019-02-06	3	-0/+247
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*	Bugfix in Verilog string handling	Clifford Wolf	2019-01-05	1	-1/+1
*	Remove -m32 Verific eval lib build instructions	Clifford Wolf	2019-01-04	1	-29/+0
*	Improve VerificImporter support for writes to asymmetric memories	Clifford Wolf	2019-01-02	1	-22/+35
*	Fix VerificImporter asymmetric memories error message	Clifford Wolf	2019-01-02	1	-1/+1
*	Fix typographical and grammatical errors and inconsistencies.	whitequark	2019-01-02	5	-11/+11
*	Add "read_ilang -[no]overwrite"	Clifford Wolf	2018-12-23	3	-4/+54
*	Fix segfault in AST simplify	Clifford Wolf	2018-12-18	1	-0/+5
*	Improve src tagging (using names and attrs) of cells and wires in verific fro...	Clifford Wolf	2018-12-18	2	-99/+160
*	read_ilang: allow slicing sigspecs.	whitequark	2018-12-16	1	-10/+6