aboutsummaryrefslogtreecommitdiffstats
path: root/frontends
Commit message (Expand)AuthorAgeFilesLines
...
* | read_aiger to ignore line after ands for ascii, not binaryEddie Hung2019-02-171-2/+1
* | Merge https://github.com/YosysHQ/yosys into read_aigerEddie Hung2019-02-171-5/+4
|\|
| * Fix sign handling of real constantsClifford Wolf2019-02-131-5/+4
* | Merge branch 'read_aiger' of github.com:eddiehung/yosys into read_aigerEddie Hung2019-02-121-3/+1
|\ \
| * | Do not break for constraintsEddie Hung2019-02-111-1/+0
| * | No increment line_count for binary ANDsEddie Hung2019-02-111-1/+1
| * | Do not ignore newline after AND in binary AIGEddie Hung2019-02-111-1/+0
* | | Use module->add{Not,And}Gate() functionsEddie Hung2019-02-121-8/+2
|/ /
* | addDff -> addDffGate as per @daveshah1Eddie Hung2019-02-081-1/+1
* | Fix tabulationEddie Hung2019-02-081-28/+28
* | -module_name arg to go before -clk_nameEddie Hung2019-02-081-7/+7
* | Add missing "[options]" to read_blif helpEddie Hung2019-02-081-1/+1
* | Allow module name to be determined by argument tooEddie Hung2019-02-082-14/+44
* | Refactor into AigerReader classEddie Hung2019-02-082-79/+92
* | Parse binary AIG filesEddie Hung2019-02-081-49/+164
* | Refactor to parse_aiger_header()Eddie Hung2019-02-081-26/+32
* | Add commentEddie Hung2019-02-081-0/+1
* | Handle reset logic in latchesEddie Hung2019-02-081-2/+17
* | Change literal vars from int to unsignedEddie Hung2019-02-081-1/+1
* | Create clk outside of latch loopEddie Hung2019-02-081-7/+9
* | Handle latch symbols tooEddie Hung2019-02-081-3/+1
* | Remove return after log_errorEddie Hung2019-02-081-27/+9
* | Add support for symbol tablesEddie Hung2019-02-081-1/+49
* | Stub for binary AIGEREddie Hung2019-02-081-3/+8
* | RefactorEddie Hung2019-02-061-1/+8
* | WIPEddie Hung2019-02-063-0/+247
|/
* Bugfix in Verilog string handlingClifford Wolf2019-01-051-1/+1
* Remove -m32 Verific eval lib build instructionsClifford Wolf2019-01-041-29/+0
* Improve VerificImporter support for writes to asymmetric memoriesClifford Wolf2019-01-021-22/+35
* Fix VerificImporter asymmetric memories error messageClifford Wolf2019-01-021-1/+1
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-025-11/+11
* Add "read_ilang -[no]overwrite"Clifford Wolf2018-12-233-4/+54
* Fix segfault in AST simplifyClifford Wolf2018-12-181-0/+5
* Improve src tagging (using names and attrs) of cells and wires in verific fro...Clifford Wolf2018-12-182-99/+160
* read_ilang: allow slicing sigspecs.whitequark2018-12-161-10/+6
* verilog_parser: Properly handle recursion when processing attributesSylvain Munaut2018-12-141-19/+29
* Verific updatesClifford Wolf2018-12-061-53/+0
* Make return value of $clog2 signedSylvain Munaut2018-11-241-1/+1
* Set Verific flag vhdl_support_variable_slice=1Clifford Wolf2018-11-091-0/+1
* Allow square brackets in liberty identifiersClifford Wolf2018-11-051-1/+2
* Add warning for SV "restrict" without "property"Clifford Wolf2018-11-041-2/+11
* Various indenting fixes in AST front-end (mostly space vs tab issues)Clifford Wolf2018-11-043-99/+69
* Make and dependent upon LSB onlyZipCPU2018-11-031-2/+8
* Do not generate "reg assigned in a continuous assignment" warnings for "rand ...Clifford Wolf2018-11-011-2/+15
* Fix minor typo in error messageClifford Wolf2018-10-251-1/+1
* Merge pull request #679 from udif/pr_syntax_errorClifford Wolf2018-10-251-14/+14
|\
| * Rename the generic "Syntax error" message from the Verilog/SystemVerilog pars...Udi Finkelstein2018-10-251-14/+14
* | Improve read_verilog range out of bounds warningClifford Wolf2018-10-201-6/+6
* | Refactor code to avoid code duplication + added commentsRuben Undheim2018-10-203-134/+108
* | Support for SystemVerilog interfaces as a port in the top level module + test...Ruben Undheim2018-10-201-3/+105
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-25 00:05:16 +0000