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* | | | Verific: Produce errors for instantiating unknown moduleClifford Wolf2018-07-221-0/+3
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* | | Convert more log_error() to log_file_error() where possible.Henner Zeller2018-07-204-137/+131
* | | Use log_file_warning(), log_file_error() functions.Henner Zeller2018-07-203-82/+79
* | | Provide source-location logging.Henner Zeller2018-07-191-3/+2
* | | Fix handling of eventually properties in verific importerClifford Wolf2018-07-171-2/+4
* | | Fix verific -vlog-incdir and -vlog-libdir handlingClifford Wolf2018-07-161-2/+13
* | | Fix "read -incdir"Clifford Wolf2018-07-161-1/+1
* | | Add "read -incdir"Clifford Wolf2018-07-161-0/+19
* | | Fix verific eventually handlingClifford Wolf2018-06-291-6/+5
* | | Add verific support for eventually propertiesClifford Wolf2018-06-291-5/+105
* | | Add "verific -formal" and "read -formal"Clifford Wolf2018-06-291-7/+15
* | | Add "read -sv -D" supportClifford Wolf2018-06-281-2/+25
* | | Add "read -undef"Clifford Wolf2018-06-281-0/+32
* | | Fix handling of signed memoriesClifford Wolf2018-06-281-0/+3
* | | Add YOSYS_NOVERIFIC env variable for temporarily disabling verificClifford Wolf2018-06-221-22/+40
* | | Add simplified "read" command, enable extnets in implicit Verific importClifford Wolf2018-06-211-0/+84
* | | Add automatic verific import in hierarchy commandClifford Wolf2018-06-202-0/+56
* | | Bugfix in liberty parser (as suggested by aiju in #569)Clifford Wolf2018-06-151-1/+1
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* | Add (* gclk *) attribute supportClifford Wolf2018-06-013-0/+20
* | Add comment to VIPER #13453 work-aroundClifford Wolf2018-05-281-0/+1
* | Fix Verific handling of single-bit anyseq/anyconst wiresClifford Wolf2018-05-251-2/+4
* | Fix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGEClifford Wolf2018-05-241-1/+1
* | Fix verific handling of anyconst/anyseq attributesClifford Wolf2018-05-242-16/+28
* | Support SystemVerilog `` extension for macrosJim Paris2018-05-171-1/+5
* | Skip spaces around macro argumentsJim Paris2018-05-171-0/+1
* | Fix handling of anyconst/anyseq attrs in VHDL code via VerificClifford Wolf2018-05-151-6/+6
* | Also interpret '&' in liberty functionsSergiusz Bazanski2018-05-121-1/+1
* | Further improve handling of zero-length SVA consecutive repetitionClifford Wolf2018-05-051-69/+108
* | Fix handling of zero-length SVA consecutive repetitionClifford Wolf2018-05-051-26/+46
* | Replace -ignore_redef with -[no]overwriteClifford Wolf2018-05-034-19/+56
* | Support more character literalsDan Gisselquist2018-05-031-1/+9
* | Add statement labels for immediate assertionsClifford Wolf2018-04-131-18/+21
* | Allow "property" in immediate assertionsClifford Wolf2018-04-121-17/+20
* | Add PRIM_HDL_ASSERTION support to Verific importerClifford Wolf2018-04-071-3/+19
* | Fix handling of $global_clocking in VerificClifford Wolf2018-04-061-1/+7
* | Add read_verilog anyseq/anyconst/allseq/allconst attribute supportClifford Wolf2018-04-061-1/+33
* | Add Verific anyseq/anyconst/allseq/allconst attribute supportClifford Wolf2018-04-061-2/+36
* | Add "verific -autocover"Clifford Wolf2018-04-062-5/+17
* | Set RAM runtime flags for Verific frontendmakaimann2018-04-051-0/+3
* | Remove left-over log_ping debug commands.. oops.Clifford Wolf2018-03-311-4/+0
* | First draft of Verilog parser support for specify blocks and parameters.Udi Finkelstein2018-03-272-2/+170
* | Fix handling of unclocked immediate assertions in Verific front-endClifford Wolf2018-03-263-17/+42
* | Update todo for more features to verificsva.ccClifford Wolf2018-03-161-3/+3
* | Update todo for more features to verificsva.ccClifford Wolf2018-03-161-0/+1
* | Add todo for more features to verificsva.ccClifford Wolf2018-03-161-8/+45
* | Improve import of memories via VerificClifford Wolf2018-03-151-16/+23
* | Fix handling of SV compilation units in Verific front-endClifford Wolf2018-03-141-28/+25
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* Fix SVA handling of NON_CONSECUTIVE_REPEAT and GOTO_REPEATClifford Wolf2018-03-101-15/+72
* Fix variable name typo in verificsva.ccClifford Wolf2018-03-101-2/+2
* Add support for trivial SVA sequences and propertiesClifford Wolf2018-03-101-12/+102
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