iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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* \|	Tidy up	Eddie Hung	2019-04-22	1	-1/+1
* \|	Revert "Temporarily remove 'r' extension"	Eddie Hung	2019-04-22	1	-0/+18
* \|	Temporarily remove 'r' extension	Eddie Hung	2019-04-22	1	-18/+0
* \|	Merge remote-tracking branch 'origin/master' into xaig	Eddie Hung	2019-04-22	2	-7/+38
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\| *	Merge pull request #952 from YosysHQ/clifford/fix370	Clifford Wolf	2019-04-22	1	-3/+18
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\| \| *	Determine correct signedness and expression width in for loop unrolling, fixe...	Clifford Wolf	2019-04-22	1	-3/+18
\| * \|	Add log_debug() framework	Clifford Wolf	2019-04-22	1	-2/+0
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\| *	Merge pull request #909 from zachjs/master	Clifford Wolf	2019-04-22	1	-1/+20
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\| \| *	support repeat loops with constant repeat counts outside of constant functions	Zachary Snow	2019-04-09	1	-1/+20
* \| \|	Merge remote-tracking branch 'origin/clifford/libwb' into xaig	Eddie Hung	2019-04-21	5	-35/+111
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\| * \|	Add "noblackbox" attribute	Clifford Wolf	2019-04-21	1	-17/+27
\| * \|	New behavior for front-end handling of whiteboxes	Clifford Wolf	2019-04-20	5	-34/+100
* \| \|	read_aiger to parse 'r' extension	Eddie Hung	2019-04-18	1	-0/+18
* \| \|	Merge remote-tracking branch 'origin/clifford/whitebox' into xaig	Eddie Hung	2019-04-18	5	-11/+42
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\| * \|	Add "whitebox" attribute, add "read_verilog -wb"	Clifford Wolf	2019-04-18	5	-11/+42
* \| \|	Ignore a/i/o/h XAIGER extensions	Eddie Hung	2019-04-17	1	-0/+7
* \| \|	Forgot backslashes	Eddie Hung	2019-04-12	1	-1/+1
* \| \|	Handle __dummy_o__ and __const[01]__ in read_aiger not abc	Eddie Hung	2019-04-12	1	-0/+4
* \| \|	Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig	Eddie Hung	2019-04-12	1	-12/+32
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\| * \| \|	Fix inout handling for -map option	Eddie Hung	2019-04-12	1	-10/+30
* \| \| \|	Also cope with duplicated CIs	Eddie Hung	2019-04-12	1	-5/+23
* \| \| \|	Cope with an output having same name as an input (i.e. CO)	Eddie Hung	2019-04-12	1	-5/+23
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* \| \|	parse_aiger() to rename all $lut cells after "clean"	Eddie Hung	2019-04-10	1	-24/+21
* \| \|	Fix spacing	Eddie Hung	2019-04-08	1	-29/+29
* \| \|	Merge branch 'master' into xaig	Eddie Hung	2019-04-08	15	-142/+500
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\| * \|	Add "read_ilang -lib"	Clifford Wolf	2019-04-05	3	-3/+14
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\| *	Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906	Clifford Wolf	2019-03-29	1	-0/+2
\| *	Add "read -verific" and "read -noverific"	Clifford Wolf	2019-03-27	1	-6/+28
\| *	Fix "verific -extnets" for more complex situations	Clifford Wolf	2019-03-26	1	-15/+71
\| *	Fix mem2reg handling of memories with upto data ports, fixes #888	Clifford Wolf	2019-03-21	1	-1/+10
\| *	Improve "read_verilog -dump_vlog[12]" handling of upto ranges	Clifford Wolf	2019-03-21	1	-3/+6
\| *	Improve read_verilog debug output capabilities	Clifford Wolf	2019-03-21	3	-15/+42
\| *	Merge https://github.com/YosysHQ/yosys into read_aiger	Eddie Hung	2019-03-19	8	-110/+348
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\| \| *	fix local name resolution in prefix constructs	Zachary Snow	2019-03-18	1	-1/+5
\| \| *	Improve handling of "full_case" attributes	Clifford Wolf	2019-03-14	1	-0/+9
\| \| *	Improve handling of memories used in mem index expressions on LHS of an assig...	Clifford Wolf	2019-03-12	1	-5/+16
\| \| *	Remove outdated "blocking assignment to memory" warning	Clifford Wolf	2019-03-12	1	-10/+0
\| \| *	Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867	Clifford Wolf	2019-03-12	1	-6/+8
\| \| *	Fix handling of cases that look like sva labels, fixes #862	Clifford Wolf	2019-03-10	2	-92/+66
\| \| *	Merge pull request #858 from YosysHQ/clifford/svalabels	Clifford Wolf	2019-03-09	5	-56/+201
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\| \| \| *	Also add support for labels on sva module items, fixes #699	Clifford Wolf	2019-03-08	2	-44/+113
\| \| \| *	Add support for SVA labels in read_verilog	Clifford Wolf	2019-03-07	3	-26/+89
\| \| \| *	Add hack for handling SVA labels via Verific	Clifford Wolf	2019-03-07	1	-1/+14
\| \| * \|	Update help message for -chparam	Eddie Hung	2019-03-09	1	-1/+2
\| \| * \|	Add -chparam option to verific command	Eddie Hung	2019-03-09	1	-2/+18
\| \| * \|	Fix spelling	Eddie Hung	2019-03-09	1	-1/+1
\| \| * \|	Fix handling of task output ports in clocked always blocks, fixes #857	Clifford Wolf	2019-03-07	1	-15/+18
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\| \| *	Merge pull request #848 from YosysHQ/clifford/fix763	Clifford Wolf	2019-03-02	1	-1/+5
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\| \| \| *	Fix error for wire decl in always block, fixes #763	Clifford Wolf	2019-03-02	1	-1/+5
\| \| * \|	Only run derive on blackbox modules when ports have dynamic size	Clifford Wolf	2019-03-02	2	-0/+20
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