Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Merge pull request #2188 from antmicro/missing-operators | whitequark | 2020-06-26 | 2 | -2/+49 |
|\ | | | | | Add logic-assignments operators | ||||
| * | Support missing sub-assign and and-assign operators | Kamil Rakoczy | 2020-06-25 | 2 | -2/+21 |
| | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com> | ||||
| * | Support missing xor-assign operator | Lukasz Dalek | 2020-06-24 | 2 | -1/+10 |
| | | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com> | ||||
| * | Add plus-assignment operator | Kamil Rakoczy | 2020-06-24 | 2 | -1/+10 |
| | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com> | ||||
| * | Add or-assignment operator | Kamil Rakoczy | 2020-06-24 | 2 | -1/+11 |
| | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com> | ||||
* | | Merge pull request #2189 from antmicro/optional-labels | whitequark | 2020-06-26 | 1 | -2/+2 |
|\ \ | | | | | | | Add support for optional labels | ||||
| * | | Support optional labels at the end of package definition | Lukasz Dalek | 2020-06-24 | 1 | -1/+1 |
| | | | | | | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com> | ||||
| * | | Support optional labels at the end of module definition | Lukasz Dalek | 2020-06-24 | 1 | -1/+1 |
| |/ | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com> | ||||
* | | Merge pull request #2168 from whitequark/assert-unused-exprs | clairexen | 2020-06-25 | 3 | -12/+12 |
|\ \ | | | | | | | Use (and ignore) the expression provided to log_assert in NDEBUG builds | ||||
| * | | Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug(). | whitequark | 2020-06-19 | 3 | -12/+12 |
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* | | optimization, all items should have same attributes | Miodrag Milanovic | 2020-06-25 | 1 | -0/+1 |
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* | | verific - import attributes for net buses as well | Miodrag Milanovic | 2020-06-24 | 1 | -1/+4 |
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* | Use C++11 final/override keywords. | whitequark | 2020-06-18 | 9 | -34/+34 |
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* | MSVC does not understand __builtin_unreachable | Anonymous Maarten | 2020-06-17 | 1 | -1/+1 |
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* | MSVC cannot omit operand in conditional | Anonymous Maarten | 2020-06-17 | 1 | -1/+1 |
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* | Merge pull request #2131 from YosysHQ/claire/preserveffs | clairexen | 2020-06-10 | 1 | -0/+3 |
|\ | | | | | Do not optimize away FFs in "prep" and Verific front-end | ||||
| * | Do not optimize away FFs in "prep" and Verific fron-end | Claire Wolf | 2020-06-09 | 1 | -0/+3 |
| | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com> | ||||
* | | verific - detect missing memory to prevent crash. | Miodrag Milanovic | 2020-06-10 | 1 | -2/+7 |
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* | | Merge pull request #2112 from YosysHQ/claire/fix2040 | clairexen | 2020-06-09 | 2 | -0/+58 |
|\ \ | |/ |/| | Add latch detection for use_case_method in part-select write | ||||
| * | Add latch detection for use_case_method in part-select write, fixes #2040 | Claire Wolf | 2020-06-04 | 2 | -0/+58 |
| | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com> | ||||
* | | Support packed arrays in struct/union. | Peter Crozier | 2020-06-07 | 2 | -17/+136 |
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* | Merge pull request #2041 from PeterCrozier/struct | clairexen | 2020-06-04 | 6 | -204/+526 |
|\ | | | | | Implementation of SV structs. | ||||
| * | Merge branch 'master' into struct | Peter Crozier | 2020-06-03 | 8 | -53/+95 |
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| * | | Allow structs within structs. | Peter Crozier | 2020-05-12 | 1 | -7/+18 |
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| * | | Generalise structs and add support for packed unions. | Peter Crozier | 2020-05-12 | 6 | -58/+147 |
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| * | | Implement SV structs. | Peter Crozier | 2020-05-08 | 6 | -205/+427 |
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* | | | Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve | Eddie Hung | 2020-06-04 | 1 | -2/+5 |
|\ \ \ | | | | | | | | | abc9: -dff improvements | ||||
| * | | | aiger: cleanup | Eddie Hung | 2020-05-25 | 1 | -2/+5 |
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* | | | | Merge pull request #2006 from jersey99/signed-in-rtlil-wire | whitequark | 2020-06-04 | 3 | -1/+10 |
|\ \ \ \ | |_|_|/ |/| | | | Preserve 'signed'-ness of a verilog wire through RTLIL | ||||
| * | | | frontends/json/jsonparse.cc: Like the upto field read_json can also read the ↵ | Vamsi K Vytla | 2020-04-27 | 1 | -1/+6 |
| | | | | | | | | | | | | | | | | signedness of a wire | ||||
| * | | | Preserve 'signed'-ness of a verilog wire through RTLIL | Vamsi K Vytla | 2020-04-27 | 2 | -0/+4 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now: RTLIL::wire holds an is_signed field. This is exported in JSON backend This is exported via dump_rtlil command This is read in via ilang_parser | ||||
* | | | | Support asymmetric memories for verific frontend | Miodrag Milanovic | 2020-06-01 | 1 | -6/+1 |
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* | | | | Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logic | clairexen | 2020-05-29 | 1 | -2/+2 |
|\ \ \ \ | | | | | | | | | | | ast/simplify: don't bitblast async ROMs declared as `logic` | ||||
| * | | | | ast/simplify: don't bitblast async ROMs declared as `logic`. | whitequark | 2020-05-05 | 1 | -2/+2 |
| | | | | | | | | | | | | | | | | | | | | Fixes #2020. | ||||
* | | | | | Merge pull request #2097 from whitequark/ilang_lexer-fix-erange | whitequark | 2020-05-29 | 1 | -1/+3 |
|\ \ \ \ \ | | | | | | | | | | | | | ilang_lexer: fix check for out of range literal | ||||
| * | | | | | ilang_lexer: fix check for out of range literal. | whitequark | 2020-05-29 | 1 | -1/+3 |
| | | | | | | | | | | | | | | | | | | | | | | | | Commit ca70a104 did not use a correct check. | ||||
* | | | | | | Merge pull request #2033 from boqwxp/cleanup-verilog-lexer | whitequark | 2020-05-29 | 1 | -6/+5 |
|\ \ \ \ \ \ | |/ / / / / |/| | | | | | verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace. | ||||
| * | | | | | verilog: Move lexer location variables from global namespace to ↵ | Alberto Gonzalez | 2020-05-06 | 1 | -6/+5 |
| | | | | | | | | | | | | | | | | | | | | | | | | `VERILOG_FRONTEND` namespace. | ||||
* | | | | | | Silence spurious warning in Verilog lexer when compiling with GCC | Rupert Swarbrick | 2020-05-26 | 1 | -1/+3 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The chosen value shouldn't have any effect. I considered something clearly wrong like -1, but there's no checking inside the generated lexer, and I suspect this will cause even weirder bugs if triggered than just setting it to INITIAL. | ||||
* | | | | | | verilog: move attr from simple_behav_stmt to its children to attach | Eddie Hung | 2020-05-25 | 1 | -13/+17 |
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* | | | | | | verilog: do not warn for attributes on null statements | Eddie Hung | 2020-05-25 | 1 | -2/+0 |
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* | | | | | | verilog: handle empty generate statement by removing gen_stmt_or_null... | Eddie Hung | 2020-05-25 | 1 | -7/+8 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ... rule which causes a s/r conflict. Now we get an empty genblock, which should be okay. | ||||
* | | | | | | verilog: fix #2037 by permitting (and freeing) attributes on null stmt | Eddie Hung | 2020-05-25 | 1 | -1/+5 |
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* | | | | | Merge pull request #2057 from YosysHQ/eddie/fix_task_attr | Eddie Hung | 2020-05-21 | 1 | -11/+9 |
|\ \ \ \ \ | | | | | | | | | | | | | verilog: support attributes before (not after) task identifier (but 13 s/r conflicts) | ||||
| * | | | | | Update frontends/verilog/verilog_parser.y | Eddie Hung | 2020-05-21 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | | | Co-authored-by: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com> | ||||
| * | | | | | verilog: attributes before task enable (but 13 s/r conflicts) | Eddie Hung | 2020-05-14 | 1 | -10/+8 |
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* | | | | | Add force_downto and force_upto wire attributes. | Marcelina Kościelnicka | 2020-05-19 | 2 | -1/+20 |
| | | | | | | | | | | | | | | | | | | | | Fixes #2058. | ||||
* | | | | | Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff | Eddie Hung | 2020-05-18 | 2 | -4/+12 |
|\ \ \ \ \ | | | | | | | | | | | | | abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *) | ||||
| * | | | | | aiger: -xaiger to return $_FF_ flops | Eddie Hung | 2020-05-14 | 1 | -15/+2 |
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| * | | | | | aiger/xaiger: use odd for negedge clk, even for posedge | Eddie Hung | 2020-05-14 | 1 | -4/+3 |
| | | | | | | | | | | | | | | | | | | | | | | | | Since abc9 doesn't like negative mergeability values |