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* Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-241-0/+12
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| * Add upto and offset to JSON portsMiodrag Milanovic2019-06-211-0/+12
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* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-213-6/+19
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| * Fix typoMiodrag Milanovic2019-06-211-1/+1
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| * Added JSON upto and offsetClifford Wolf2019-06-211-0/+12
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge pull request #1119 from YosysHQ/eddie/fix1118Clifford Wolf2019-06-211-0/+1
| |\ | | | | | | Make genvar a signed type
| | * Make genvar a signed typeEddie Hung2019-06-201-0/+1
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| * | Maintain "is_unsized" state of constantsEddie Hung2019-06-201-6/+6
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* | Reduce log_debug spam in parse_xaiger()Eddie Hung2019-06-211-16/+19
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* | Workaround issues exposed by gcc-4.8Eddie Hung2019-06-211-0/+7
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* | Fix broken abc9.v test due to inout being 1'bxEddie Hung2019-06-201-3/+10
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* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-206-15/+77
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| * Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into ↵Clifford Wolf2019-06-201-1/+7
| |\ | | | | | | | | | towoe-unpacked_arrays
| | * Unpacked array declaration using sizeTobias Wölfel2019-06-191-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | Allows fixed-sized array dimension specified by a single number. This commit is based on the work from PeterCrozier https://github.com/YosysHQ/yosys/pull/560. But is split out of the original work.
| * | Add "read_verilog -pwires" feature, closes #1106Clifford Wolf2019-06-195-9/+44
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add defaultvalue attributeClifford Wolf2019-06-191-0/+11
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Fix handling of "logic" variables with initial valueClifford Wolf2019-06-191-2/+2
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Fixed brojen $error()/$info/$warning() on non-generate blocksUdi Finkelstein2019-06-112-3/+13
| |/ | | | | | | (within always/initial blocks)
* | Fix issue with part of PI being 1'bxEddie Hung2019-06-201-4/+6
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* | CleanupEddie Hung2019-06-161-20/+1
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* | Cover __APPLE__ too for little to big endianEddie Hung2019-06-141-4/+7
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* | Further cleanup based on @daveshah1Eddie Hung2019-06-141-10/+20
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* | Resolve comments from @daveshah1Eddie Hung2019-06-141-2/+2
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* | CleanupEddie Hung2019-06-141-7/+3
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* | Add TODO to parse_xaigerEddie Hung2019-06-141-0/+1
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* | Optimise some moreEddie Hung2019-06-131-58/+53
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* | Move ConstEvalAig to aigerparse.ccEddie Hung2019-06-131-3/+161
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* | Add ConstEvalAig specialised for AIGsEddie Hung2019-06-131-3/+2
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* | parse_xaiger to cope with inoutsEddie Hung2019-06-121-6/+0
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* | ConsistencyEddie Hung2019-06-122-2/+2
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* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-1216-957/+1462
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| * Fix spacing from spaces to tabsEddie Hung2019-06-071-362/+362
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| * Fix spacing (entire file is wrong anyway, will fix later)Eddie Hung2019-06-071-3/+3
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| * Remove unnecessary std::getline() for ASCIIEddie Hung2019-06-071-3/+0
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| * Fix read_aiger -- create zero driver, fix init width, parse 'b'Eddie Hung2019-06-072-13/+52
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| * Fixes and cleanups in AST_TECALL handlingClifford Wolf2019-06-073-46/+34
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵Clifford Wolf2019-06-076-5/+64
| |\ | | | | | | | | | clifford/pr983
| | * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-036-5/+64
| | | | | | | | | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen.
| * | Cleanup tux3-implicit_named_connectionClifford Wolf2019-06-071-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys ↵Clifford Wolf2019-06-071-1/+10
| |\ \ | | | | | | | | | | | | into tux3-implicit_named_connection
| | * | SystemVerilog support for implicit named port connectionstux32019-06-061-9/+17
| | | | | | | | | | | | | | | | | | | | This is the `foo foo(.port1, .port2);` SystemVerilog syntax introduced in IEEE1800-2005.
| * | | Merge pull request #1060 from antmicro/parsing_attr_on_port_connClifford Wolf2019-06-061-10/+14
| |\ \ \ | | |/ / | |/| | Added support for parsing attributes on port connections.
| | * | Fixed memory leak.Maciej Kurc2019-06-051-0/+4
| | | | | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| | * | Added support for parsing attributes on port connections.Maciej Kurc2019-05-311-10/+10
| | | | | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * | | Only support Symbiotic EDA flavored VerificClifford Wolf2019-06-021-0/+8
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, ↵Clifford Wolf2019-05-301-0/+3
| | | | | | | | | | | | | | | | | | fixes #1055 Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge branch 'master' into wandworStefan Biereigel2019-05-275-14/+47
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| | * \ Merge pull request #1044 from mmicko/invalid_width_rangeClifford Wolf2019-05-271-1/+2
| | |\ \ | | | | | | | | | | Give error instead of asserting for invalid range, fixes #947
| | | * | Give error instead of asserting for invalid range, fixes #947Miodrag Milanovic2019-05-271-1/+2
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| | * | | Added support for unsized constants, fixes #1022Miodrag Milanovic2019-05-275-13/+45
| | |/ / | | | | | | | | | | | | Includes work from @sumit0190 and @AaronKel
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