| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Merge remote-tracking branch 'origin/master' into clifford/specify | Eddie Hung | 2019-05-03 | 1 | -2/+2 |
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| | * | Include filename in "Executing Verilog-2005 frontend" message, fixes #959 | Clifford Wolf | 2019-04-30 | 1 | -2/+2 |
| * | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 2 | -9/+19 |
| * | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 1 | -20/+18 |
| * | | Add $specrule cells for $setup/$hold/$skew specify rules | Clifford Wolf | 2019-04-23 | 2 | -2/+78 |
| * | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom... | Clifford Wolf | 2019-04-23 | 1 | -2/+2 |
| * | | Un-break default specify parser | Clifford Wolf | 2019-04-23 | 1 | -0/+1 |
| * | | Add specify parser | Clifford Wolf | 2019-04-23 | 4 | -33/+243 |
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| * | New behavior for front-end handling of whiteboxes | Clifford Wolf | 2019-04-20 | 3 | -16/+30 |
| * | Add "whitebox" attribute, add "read_verilog -wb" | Clifford Wolf | 2019-04-18 | 3 | -7/+20 |
| * | Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906 | Clifford Wolf | 2019-03-29 | 1 | -0/+2 |
| * | Improve read_verilog debug output capabilities | Clifford Wolf | 2019-03-21 | 1 | -5/+24 |
| * | Fix handling of cases that look like sva labels, fixes #862 | Clifford Wolf | 2019-03-10 | 2 | -92/+66 |
| * | Also add support for labels on sva module items, fixes #699 | Clifford Wolf | 2019-03-08 | 2 | -44/+113 |
| * | Add support for SVA labels in read_verilog | Clifford Wolf | 2019-03-07 | 1 | -23/+79 |
| * | Bugfix in Verilog string handling | Clifford Wolf | 2019-01-05 | 1 | -1/+1 |
| * | Fix typographical and grammatical errors and inconsistencies. | whitequark | 2019-01-02 | 1 | -3/+3 |
| * | verilog_parser: Properly handle recursion when processing attributes | Sylvain Munaut | 2018-12-14 | 1 | -19/+29 |
| * | Add warning for SV "restrict" without "property" | Clifford Wolf | 2018-11-04 | 1 | -2/+11 |
| * | Fix minor typo in error message | Clifford Wolf | 2018-10-25 | 1 | -1/+1 |
| * | Rename the generic "Syntax error" message from the Verilog/SystemVerilog pars... | Udi Finkelstein | 2018-10-25 | 1 | -14/+14 |
| * | Merge pull request #659 from rubund/sv_interfaces | Clifford Wolf | 2018-10-18 | 2 | -0/+88 |
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| | * | Handle FIXME for modport members without type directly in front | Ruben Undheim | 2018-10-13 | 1 | -6/+8 |
| | * | Support for 'modports' for System Verilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -3/+21 |
| | * | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 2 | -0/+68 |
| * | | ignore protect endprotect | argama | 2018-10-16 | 1 | -0/+3 |
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| * | Add "read_verilog -noassert -noassume -assert-assumes" | Clifford Wolf | 2018-09-24 | 3 | -6/+49 |
| * | Added support for ommited "parameter" in Verilog-2001 style parameter decl in... | Clifford Wolf | 2018-09-23 | 1 | -3/+9 |
| * | Add "make coverage" | Clifford Wolf | 2018-08-27 | 3 | -6/+5 |
| * | Merge pull request #610 from udif/udif_specify_round2 | Clifford Wolf | 2018-08-23 | 1 | -16/+39 |
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| | * | Fixed all known specify/endspecify issues, without breaking 'make test'. | Udi Finkelstein | 2018-08-20 | 1 | -12/+12 |
| | * | Yosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-rout... | Udi Finkelstein | 2018-08-20 | 1 | -10/+22 |
| | * | A few minor enhancements to specify block parsing. | Udi Finkelstein | 2018-08-15 | 1 | -2/+13 |
| * | | Added -no_dump_ptr flag for AST dump options in 'read_verilog' | Udi Finkelstein | 2018-08-23 | 1 | -1/+9 |
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| * | Merge pull request #591 from hzeller/virtual-override | Clifford Wolf | 2018-08-15 | 1 | -6/+6 |
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| | * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -6/+6 |
| * | | Merge pull request #513 from udif/pr_reg_wire_error | Clifford Wolf | 2018-08-15 | 2 | -2/+7 |
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| | * | | Modified errors into warnings | Udi Finkelstein | 2018-06-05 | 1 | -0/+1 |
| | * | | This PR should be the base for discussion, do not merge it yet! | Udi Finkelstein | 2018-03-11 | 2 | -2/+6 |
| * | | | Merge pull request #562 from udif/pr_fix_illegal_port_decl | Clifford Wolf | 2018-08-15 | 1 | -3/+6 |
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| | * | | Detect illegal port declaration, e.g input/output/inout keyword must be the f... | Udi Finkelstein | 2018-06-06 | 1 | -3/+6 |
| * | | | Convert more log_error() to log_file_error() where possible. | Henner Zeller | 2018-07-20 | 1 | -5/+3 |
| * | | | Use log_file_warning(), log_file_error() functions. | Henner Zeller | 2018-07-20 | 1 | -5/+3 |
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| * | | Support SystemVerilog `` extension for macros | Jim Paris | 2018-05-17 | 1 | -1/+5 |
| * | | Skip spaces around macro arguments | Jim Paris | 2018-05-17 | 1 | -0/+1 |
| * | | Replace -ignore_redef with -[no]overwrite | Clifford Wolf | 2018-05-03 | 1 | -6/+17 |
| * | | Support more character literals | Dan Gisselquist | 2018-05-03 | 1 | -1/+9 |
| * | | Add statement labels for immediate assertions | Clifford Wolf | 2018-04-13 | 1 | -18/+21 |
| * | | Allow "property" in immediate assertions | Clifford Wolf | 2018-04-12 | 1 | -17/+20 |
| * | | Add read_verilog anyseq/anyconst/allseq/allconst attribute support | Clifford Wolf | 2018-04-06 | 1 | -1/+33 |
