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* verilog: fix sizing of ports with int types in module headersZachary Snow2021-03-011-2/+3
* verilog: fix handling of nested ifdef directivesZachary Snow2021-03-011-11/+38
* Merge pull request #2523 from tomverbeure/define_synthesisClaire Xen2021-03-011-3/+12
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| * Fix indents.Tom Verbeure2021-01-041-2/+2
| * Add -nosynthesis flag for read_verilog command.Tom Verbeure2021-01-041-3/+12
* | sv: extended support for integer typesZachary Snow2021-02-282-39/+70
* | Fix handling of unique/unique0/priority cases in the frontend.Marcelina Kościelnicka2021-02-252-15/+16
* | Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and tu...TimRudy2021-02-241-2/+7
* | verilog: error on macro invocations with missing argument listsZachary Snow2021-02-191-1/+10
* | Merge pull request #2578 from zachjs/genblk-portZachary Snow2021-02-111-4/+7
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| * | verlog: allow shadowing module ports within generate blocksZachary Snow2021-02-071-4/+7
* | | Add missing is_signed to type_atomKamil Rakoczy2021-02-111-4/+4
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* | Add check of begin/end labels for genblockKamil Rakoczy2021-02-041-0/+2
* | Merge pull request #2529 from zachjs/unnamed-genblkwhitequark2021-02-041-17/+28
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| * | verilog: significant block scoping improvementsZachary Snow2021-01-311-17/+28
* | | verilog: strip leading and trailing spaces in macro argsZachary Snow2021-01-281-1/+5
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* | Merge pull request #2550 from zachjs/macro-arg-spaceswhitequark2021-01-251-1/+0
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| * | verilog: allow spaces in macro argumentsZachary Snow2021-01-201-1/+0
* | | Allow combination of rand and const modifiersZachary Snow2021-01-211-2/+10
* | | sv: fix support wire and var data type modifiersZachary Snow2021-01-201-9/+23
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* / Parse package user type in module port listLukasz Dalek2021-01-181-30/+32
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* sv: complete support for implied task/function port directionsZachary Snow2020-12-311-0/+10
* Fix SYNTHESIS always being defined in Verilog frontendgeorgerennie2020-12-012-1/+3
* Ignore empty parameters in Verilog module instantiationsClaire Xenia Wolf2020-10-011-0/+3
* Rewrite multirange arrays sizes [n] as [n-1:0]Lukasz Dalek2020-08-031-2/+11
* Treat all bison warnings as errors in verilog front-endClaire Wolf2020-07-151-1/+1
* Use %precedence in verilog_parser.yClaire Wolf2020-07-151-4/+4
* Fix bison warnings for missing %emptyClaire Wolf2020-07-151-59/+52
* Run bison with -Wall for verilog front-endClaire Wolf2020-07-151-1/+1
* Add missing semicolonsKamil Rakoczy2020-07-151-5/+5
* Fix S/R conflictsKamil Rakoczy2020-07-101-1/+2
* Fix R/R conflictsKamil Rakoczy2020-07-101-10/+1
* Revert "Revert PRs #2203 and #2244."Kamil Rakoczy2020-07-101-10/+19
* verilog_parser: turn S/R and R/R conflicts into hard errors.whitequark2020-07-091-1/+1
* Revert PRs #2203 and #2244.whitequark2020-07-091-19/+10
* Support logic typed parametersLukasz Dalek2020-07-061-7/+10
* Merge pull request #2203 from antmicro/fix-grammarclairexen2020-07-011-4/+10
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| * Parse macro call attached semicolon as empty expressionLukasz Dalek2020-06-261-1/+1
| * Fix integer signing grammarLukasz Dalek2020-06-261-3/+9
* | Merge pull request #2179 from splhack/static-castclairexen2020-07-012-0/+21
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| * | static cast: support changing size and signednessKazuki Sakamoto2020-06-192-0/+21
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* | Merge pull request #2188 from antmicro/missing-operatorswhitequark2020-06-262-2/+49
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| * | Support missing sub-assign and and-assign operatorsKamil Rakoczy2020-06-252-2/+21
| * | Support missing xor-assign operatorLukasz Dalek2020-06-242-1/+10
| * | Add plus-assignment operatorKamil Rakoczy2020-06-242-1/+10
| * | Add or-assignment operatorKamil Rakoczy2020-06-242-1/+11
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* | Support optional labels at the end of package definitionLukasz Dalek2020-06-241-1/+1
* | Support optional labels at the end of module definitionLukasz Dalek2020-06-241-1/+1
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* Use C++11 final/override keywords.whitequark2020-06-181-6/+6
* MSVC does not understand __builtin_unreachableAnonymous Maarten2020-06-171-1/+1
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