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* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-087-7/+7
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* sv: support tasks and functions within packagesZachary Snow2021-06-011-1/+1
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* sv: support remaining assignment operatorsZachary Snow2021-05-252-42/+41
| | | | | - Add support for: *=, /=, %=, <<=, >>=, <<<=, >>>= - Unify existing support for: +=, -=, &=, |=, ^=
* sv: check validity of package end labelZachary Snow2021-05-101-0/+2
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* verilog: revise hot comment warningsZachary Snow2021-03-301-6/+21
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* preproc: Fix up conditional handling.Marcelina Kościelnicka2021-03-301-3/+17
| | | | | Fixes #2710. Fixes #2711.
* verilog: check entire user type stack for type definitionXiretza2021-03-211-6/+12
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* sv: allow typenames as function return typesZachary Snow2021-03-191-0/+6
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* verilog: rebuild user_type_stack from globals before parsing fileXiretza2021-03-181-5/+21
| | | | | | | | | | | | This was actually a ticking UB bomb: after running the parser, the type maps contain pointers to children of the current AST, which is recursively deleted after the pass has executed. This leaves the pointers in user_type_stack dangling, which just happened to never be a problem due to another bug that causes typedefs from higher-level type maps to never be considered. Rebuilding the type stack from the design's globals ensures the AstNode pointers are valid.
* sv: carry over global typedefs from previous filesZachary Snow2021-03-171-2/+5
| | | | | | | This breaks the ability to use a global typename as a standard identifier in a subsequent input file. This is otherwise backwards compatible, including for sources which previously included conflicting typedefs in each input file.
* sv: support for parameters without default valuesZachary Snow2021-03-021-3/+21
| | | | | | | | | - Modules with a parameter without a default value will be automatically deferred until the hierarchy pass - Allows for parameters without defaults as module items, rather than just int the `parameter_port_list`, despite being forbidden in the LRM - Check for parameters without defaults that haven't been overriden - Add location info to parameter/localparam declarations
* verilog: fix sizing of ports with int types in module headersZachary Snow2021-03-011-2/+3
| | | | | | Declaring the ports as standard module items already worked as expected. This adds a missing usage of `checkRange()` so that headers such as `module m(output integer x);` now work correctly.
* verilog: fix handling of nested ifdef directivesZachary Snow2021-03-011-11/+38
| | | | | - track depth so we know whether to consider higher-level elsifs - error on unmatched endif/elsif/else
* Merge pull request #2523 from tomverbeure/define_synthesisClaire Xen2021-03-011-3/+12
|\ | | | | Add -nosynthesis flag for read_verilog command
| * Fix indents.Tom Verbeure2021-01-041-2/+2
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| * Add -nosynthesis flag for read_verilog command.Tom Verbeure2021-01-041-3/+12
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* | sv: extended support for integer typesZachary Snow2021-02-282-39/+70
| | | | | | | | | | | | | | | | | | - Standard data declarations can now use any integer type - Parameters and localparams can now use any integer type - Function returns types can now use any integer type - Fix `parameter logic`, `localparam reg`, etc. to be 1 bit (previously 32 bits) - Added longint type (64 bits) - Unified parser source for integer type widths
* | Fix handling of unique/unique0/priority cases in the frontend.Marcelina Kościelnicka2021-02-252-15/+16
| | | | | | | | | | | | | | | | | | | | Basically: - priority converts to (* full_case *) - unique0 converts to (* parallel_case *) - unique converts to (* parallel_case, full_case *) Fixes #2596.
* | Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and ↵TimRudy2021-02-241-2/+7
| | | | | | | | turn-off (#2566)
* | verilog: error on macro invocations with missing argument listsZachary Snow2021-02-191-1/+10
| | | | | | | | | | | | This would previously complain about an undefined internal macro if the unapplied macro had not already been used. If it had, it would incorrectly use the arguments from the previous invocation.
* | Merge pull request #2578 from zachjs/genblk-portZachary Snow2021-02-111-4/+7
|\ \ | | | | | | verlog: allow shadowing module ports within generate blocks
| * | verlog: allow shadowing module ports within generate blocksZachary Snow2021-02-071-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | This is a somewhat obscure edge case I encountered while working on test cases for earlier changes. Declarations in generate blocks should not be checked against the list of ports. This change also adds a check forbidding declarations within generate blocks being tagged as inputs or outputs.
* | | Add missing is_signed to type_atomKamil Rakoczy2021-02-111-4/+4
|/ / | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* | Add check of begin/end labels for genblockKamil Rakoczy2021-02-041-0/+2
| | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* | Merge pull request #2529 from zachjs/unnamed-genblkwhitequark2021-02-041-17/+28
|\ \ | | | | | | verilog: significant block scoping improvements
| * | verilog: significant block scoping improvementsZachary Snow2021-01-311-17/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
* | | verilog: strip leading and trailing spaces in macro argsZachary Snow2021-01-281-1/+5
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* | Merge pull request #2550 from zachjs/macro-arg-spaceswhitequark2021-01-251-1/+0
|\ \ | | | | | | verilog: allow spaces in macro arguments
| * | verilog: allow spaces in macro argumentsZachary Snow2021-01-201-1/+0
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* | | Allow combination of rand and const modifiersZachary Snow2021-01-211-2/+10
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* | | sv: fix support wire and var data type modifiersZachary Snow2021-01-201-9/+23
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* / Parse package user type in module port listLukasz Dalek2021-01-181-30/+32
|/ | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com> Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* sv: complete support for implied task/function port directionsZachary Snow2020-12-311-0/+10
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* Fix SYNTHESIS always being defined in Verilog frontendgeorgerennie2020-12-012-1/+3
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* Ignore empty parameters in Verilog module instantiationsClaire Xenia Wolf2020-10-011-0/+3
| | | | | | Fixes #2394 Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com>
* Rewrite multirange arrays sizes [n] as [n-1:0]Lukasz Dalek2020-08-031-2/+11
| | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
* Treat all bison warnings as errors in verilog front-endClaire Wolf2020-07-151-1/+1
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Use %precedence in verilog_parser.yClaire Wolf2020-07-151-4/+4
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Fix bison warnings for missing %emptyClaire Wolf2020-07-151-59/+52
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Run bison with -Wall for verilog front-endClaire Wolf2020-07-151-1/+1
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Add missing semicolonsKamil Rakoczy2020-07-151-5/+5
| | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* Fix S/R conflictsKamil Rakoczy2020-07-101-1/+2
| | | | | | This commit fixes S/R conflicts introduced by commit 6f9be93. Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* Fix R/R conflictsKamil Rakoczy2020-07-101-10/+1
| | | | | | | This commit fixes R/R conflicts introduced by commit 7e83a51. Parameter logic is already defined as part of `param_range_type` rule. Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* Revert "Revert PRs #2203 and #2244."Kamil Rakoczy2020-07-101-10/+19
| | | | This reverts commit 9c120b89ace6c111aa4677616947d18d980b9c1a.
* verilog_parser: turn S/R and R/R conflicts into hard errors.whitequark2020-07-091-1/+1
| | | | Fixes #2253.
* Revert PRs #2203 and #2244.whitequark2020-07-091-19/+10
| | | | | | | | This reverts commit 7e83a51fc96495c558a31fc3ca6c1a5ba4764f15. This reverts commit b422f2e4d0b8d5bfa97913d6b9dee488b59fc405. This reverts commit 7cb56f34b06de666935fbda315ce7c7bd45048b3. This reverts commit 6f9be939bd7653b0bdcae93a1033a086a4561b68. This reverts commit 76a34dc5f3a60c89efeaa3378ca0e2700a8aebd2.
* Support logic typed parametersLukasz Dalek2020-07-061-7/+10
| | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
* Merge pull request #2203 from antmicro/fix-grammarclairexen2020-07-011-4/+10
|\ | | | | Signed and macro grammar update
| * Parse macro call attached semicolon as empty expressionLukasz Dalek2020-06-261-1/+1
| | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
| * Fix integer signing grammarLukasz Dalek2020-06-261-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes signed/unsigned grammar in parameters as defined in SV LRM A2.2.1. Example of correct parameters: parameter integer signed i = 0; parameter integer unsigned i = 0; Example of incorrect parameters: parameter signed integer i = 0; parameter unsigned integer i = 0; Signed-off-by: Lukasz Dalek <ldalek@antmicro.com> Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
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