| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fixed supply0/supply1 with many wires | Clifford Wolf | 2014-12-11 | 1 | -3/+15 |
| * | Added warning for use of 'z' constants in HDL | Clifford Wolf | 2014-11-14 | 1 | -4/+4 |
| * | Fixed parsing of nested verilog concatenation and replicate | Clifford Wolf | 2014-11-12 | 1 | -1/+1 |
| * | Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..." | Clifford Wolf | 2014-10-30 | 1 | -4/+5 |
| * | Added support for task and function args in parentheses | Clifford Wolf | 2014-10-27 | 1 | -6/+45 |
| * | Updated lexers & parsers to include prefixes | William Speirs | 2014-10-15 | 1 | -0/+1434 |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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