| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Option to disable verific VHDL support | Miodrag Milanovic | 2021-10-20 | 1 | -0/+2 |
| * | Move Verific SVA importer to extra C++ source file | Clifford Wolf | 2018-02-18 | 1 | -0/+2 |
| * | Fix permissions on verific vdb files | Clifford Wolf | 2018-01-28 | 1 | -0/+1 |
| * | Changes for Verific 3.16_484_32_151112 | Clifford Wolf | 2015-11-12 | 1 | -2/+3 |
| * | Fixed verific bindings for new RTLIL api | Clifford Wolf | 2014-07-27 | 1 | -5/+5 |
| * | Copy Verific vdbs files to Yosys "share" data directory | Clifford Wolf | 2014-03-13 | 1 | -0/+15 |
| * | Added "verific" command | Clifford Wolf | 2014-03-09 | 1 | -0/+1 |
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index : iCE40/yosys | |
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