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* Merge pull request #2006 from jersey99/signed-in-rtlil-wirewhitequark2020-06-041-0/+3
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| * Preserve 'signed'-ness of a verilog wire through RTLILVamsi K Vytla2020-04-271-0/+3
* | frontend: cleanup to use more ID::*, more dict<> instead of map<>Eddie Hung2020-05-041-3/+3
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* ilang, ast: Store parameter order and default value information.Marcelina Koƛcielnicka2020-04-211-2/+9
* Clean up pseudo-private member usage in `frontends/ilang/ilang_parser.y`.Alberto Gonzalez2020-04-131-4/+4
* read_ilang: improve error message for overly long wires.whitequark2020-04-061-0/+3
* read_ilang: do bounds checking on bit indicesMarcin Koƛcielnicki2019-11-271-0/+4
* Allow attributes on individual switch cases in RTLIL.whitequark2019-07-081-4/+9
* Make the generated *.tab.hh include all the headers needed to define the union.Henner Zeller2019-05-141-1/+9
* Merge pull request #946 from YosysHQ/clifford/specifyClifford Wolf2019-05-061-1/+7
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| * Add "real" keyword to ilang formatClifford Wolf2019-05-061-1/+7
* | Fix the other bison warning in ilang_parser.yClifford Wolf2019-05-061-1/+1
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* Add "read_ilang -lib"Clifford Wolf2019-04-051-2/+4
* Add "read_ilang -[no]overwrite"Clifford Wolf2018-12-231-3/+23
* read_ilang: allow slicing sigspecs.whitequark2018-12-161-10/+6
* Added avail params to ilang format, check module params in 'hierarchy -check'Clifford Wolf2016-10-221-1/+7
* Added $global_clock verilog syntax support for creating $ff cellsClifford Wolf2016-10-141-1/+7
* Fixed oom bug in ilang parserClifford Wolf2015-11-291-2/+2
* Fixed performance bug in ilang parserClifford Wolf2015-11-271-6/+12
* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-251-1/+1
* Adjust makefiles to work with out-of-tree buildsClifford Wolf2015-08-121-1/+1
* Fixed trailing whitespacesClifford Wolf2015-07-021-2/+2
* Fixed memory->start_offset handlingClifford Wolf2015-01-011-0/+3
* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-261-1/+1
* Updated lexers & parsers to include prefixesWilliam Speirs2014-10-151-0/+409