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* Merge pull request #858 from YosysHQ/clifford/svalabelsClifford Wolf2019-03-092-3/+10
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| * Add support for SVA labels in read_verilogClifford Wolf2019-03-072-3/+10
* | Fix handling of task output ports in clocked always blocks, fixes #857Clifford Wolf2019-03-071-15/+18
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* Merge pull request #848 from YosysHQ/clifford/fix763Clifford Wolf2019-03-021-1/+5
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| * Fix error for wire decl in always block, fixes #763Clifford Wolf2019-03-021-1/+5
* | Only run derive on blackbox modules when ports have dynamic sizeClifford Wolf2019-03-022-0/+20
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* Fix $global_clock handling vs autowireClifford Wolf2019-03-021-1/+1
* Fix $readmem[hb] for mem2reg memories, fixes #785Clifford Wolf2019-03-021-0/+35
* Use mem2reg on memories that only have constant-index write portsClifford Wolf2019-03-012-0/+13
* Fix handling of defparam for when default_nettype is noneClifford Wolf2019-02-241-0/+4
* Fixes related to handling of autowires and upto-ranges, fixes #814Clifford Wolf2019-02-212-9/+12
* Fix handling of expression width in $past, fixes #810Clifford Wolf2019-02-211-1/+1
* Fix segfault in printing of some internal error messagesClifford Wolf2019-02-211-2/+2
* Fix sign handling of real constantsClifford Wolf2019-02-131-5/+4
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-2/+2
* Fix segfault in AST simplifyClifford Wolf2018-12-181-0/+5
* Make return value of $clog2 signedSylvain Munaut2018-11-241-1/+1
* Various indenting fixes in AST front-end (mostly space vs tab issues)Clifford Wolf2018-11-043-99/+69
* Make and dependent upon LSB onlyZipCPU2018-11-031-2/+8
* Do not generate "reg assigned in a continuous assignment" warnings for "rand ...Clifford Wolf2018-11-011-2/+15
* Improve read_verilog range out of bounds warningClifford Wolf2018-10-201-6/+6
* Refactor code to avoid code duplication + added commentsRuben Undheim2018-10-203-134/+108
* Support for SystemVerilog interfaces as a port in the top level module + test...Ruben Undheim2018-10-201-3/+105
* Fixed memory leakRuben Undheim2018-10-201-0/+1
* Merge pull request #659 from rubund/sv_interfacesClifford Wolf2018-10-184-14/+265
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| * Documentation improvements etc.Ruben Undheim2018-10-132-8/+35
| * Fix build error with clangRuben Undheim2018-10-121-1/+1
| * Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-123-5/+68
| * Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-124-14/+175
* | Merge pull request #638 from udif/pr_reg_wire_errorClifford Wolf2018-10-171-0/+12
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| * Fixed issue #630 by fixing a minor typo in the previous commitUdi Finkelstein2018-09-251-2/+2
| * Merge branch 'master' into pr_reg_wire_errorUdi Finkelstein2018-09-184-237/+254
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| * | Fixed remaining cases where we check fo wire reg/wire incorrect assignmentsUdi Finkelstein2018-09-181-0/+12
* | | Fix for issue 594.Tom Verbeure2018-10-021-1/+2
* | | Add read_verilog $changed supportDan Gisselquist2018-10-011-1/+4
* | | Fix handling of $past 2nd argument in read_verilogClifford Wolf2018-09-301-1/+1
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* | Added -no_dump_ptr flag for AST dump options in 'read_verilog'Udi Finkelstein2018-08-232-8/+11
* | Merge pull request #591 from hzeller/virtual-overrideClifford Wolf2018-08-151-4/+4
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| * | Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-4/+4
* | | Merge pull request #590 from hzeller/remaining-file-errorClifford Wolf2018-08-151-15/+15
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| * | | Fix remaining log_file_error(); emit dependent file references in new line.Henner Zeller2018-07-201-15/+15
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* | | Merge pull request #513 from udif/pr_reg_wire_errorClifford Wolf2018-08-153-2/+50
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| * Modified errors into warningsUdi Finkelstein2018-06-053-7/+40
| * This PR should be the base for discussion, do not merge it yet!Udi Finkelstein2018-03-113-2/+17
* | Convert more log_error() to log_file_error() where possible.Henner Zeller2018-07-203-132/+128
* | Use log_file_warning(), log_file_error() functions.Henner Zeller2018-07-202-77/+76
* | Provide source-location logging.Henner Zeller2018-07-191-3/+2
* | Fix handling of signed memoriesClifford Wolf2018-06-281-0/+3
* | Add (* gclk *) attribute supportClifford Wolf2018-06-011-0/+9
* | Replace -ignore_redef with -[no]overwriteClifford Wolf2018-05-032-6/+14
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