| Commit message (Expand) | Author | Age | Files | Lines |
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| * | genrtlil: emit \src attribute on CaseRule. | whitequark | 2019-07-08 | 1 | -0/+1 |
| * | Add "read_verilog -pwires" feature, closes #1106 | Clifford Wolf | 2019-06-19 | 3 | -6/+29 |
| * | Fixes and cleanups in AST_TECALL handling | Clifford Wolf | 2019-06-07 | 3 | -46/+34 |
| * | Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo... | Clifford Wolf | 2019-06-07 | 4 | -4/+49 |
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| | * | Initial implementation of elaboration system tasks | Udi Finkelstein | 2019-05-03 | 4 | -4/+49 |
| * | | Merge branch 'master' into wandwor | Stefan Biereigel | 2019-05-27 | 3 | -5/+28 |
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| | * \ | Merge pull request #1044 from mmicko/invalid_width_range | Clifford Wolf | 2019-05-27 | 1 | -1/+2 |
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| | | * | | Give error instead of asserting for invalid range, fixes #947 | Miodrag Milanovic | 2019-05-27 | 1 | -1/+2 |
| | * | | | Added support for unsized constants, fixes #1022 | Miodrag Milanovic | 2019-05-27 | 3 | -4/+26 |
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| * | | | remove leftovers from ast data structures | Stefan Biereigel | 2019-05-27 | 2 | -4/+0 |
| * | | | move wand/wor resolution into hierarchy pass | Stefan Biereigel | 2019-05-27 | 1 | -97/+14 |
| * | | | fix assignment of non-wires | Stefan Biereigel | 2019-05-23 | 1 | -16/+19 |
| * | | | fix indentation across files | Stefan Biereigel | 2019-05-23 | 3 | -61/+81 |
| * | | | implementation for assignments working | Stefan Biereigel | 2019-05-23 | 3 | -14/+83 |
| * | | | make lexer/parser aware of wand/wor net types | Stefan Biereigel | 2019-05-23 | 1 | -1/+1 |
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| * | | Merge pull request #946 from YosysHQ/clifford/specify | Clifford Wolf | 2019-05-06 | 2 | -1/+30 |
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| | * | | Improve write_verilog specify support | Clifford Wolf | 2019-05-04 | 1 | -0/+3 |
| | * | | Merge remote-tracking branch 'origin/master' into clifford/specify | Eddie Hung | 2019-05-03 | 2 | -0/+12 |
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| | * | | | Add $specrule cells for $setup/$hold/$skew specify rules | Clifford Wolf | 2019-04-23 | 2 | -2/+8 |
| | * | | | Allow $specify[23] cells in blackbox modules | Clifford Wolf | 2019-04-23 | 1 | -0/+6 |
| | * | | | Checking and fixing specify cells in genRTLIL | Clifford Wolf | 2019-04-23 | 1 | -1/+15 |
| * | | | | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968 | Clifford Wolf | 2019-05-06 | 2 | -0/+3 |
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| | * | | | Add splitcmplxassign test case and silence splitcmplxassign warning | Clifford Wolf | 2019-05-01 | 1 | -0/+1 |
| | * | | | Fix width detection of memory access with bit slice, fixes #974 | Clifford Wolf | 2019-05-01 | 1 | -0/+2 |
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| * / | | Re-enable "final loop assignment" feature | Clifford Wolf | 2019-05-01 | 1 | -2/+0 |
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| * | | Disabled "final loop assignment" feature | Clifford Wolf | 2019-04-30 | 1 | -0/+2 |
| * | | Add final loop variable assignment when unrolling for-loops, fixes #968 | Clifford Wolf | 2019-04-30 | 1 | -0/+7 |
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| * | Determine correct signedness and expression width in for loop unrolling, fixe... | Clifford Wolf | 2019-04-22 | 1 | -3/+18 |
| * | Merge pull request #909 from zachjs/master | Clifford Wolf | 2019-04-22 | 1 | -1/+20 |
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| | * | support repeat loops with constant repeat counts outside of constant functions | Zachary Snow | 2019-04-09 | 1 | -1/+20 |
| * | | Add "noblackbox" attribute | Clifford Wolf | 2019-04-21 | 1 | -17/+27 |
| * | | New behavior for front-end handling of whiteboxes | Clifford Wolf | 2019-04-20 | 2 | -18/+70 |
| * | | Add "whitebox" attribute, add "read_verilog -wb" | Clifford Wolf | 2019-04-18 | 2 | -4/+22 |
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| * | Fix mem2reg handling of memories with upto data ports, fixes #888 | Clifford Wolf | 2019-03-21 | 1 | -1/+10 |
| * | Improve "read_verilog -dump_vlog[12]" handling of upto ranges | Clifford Wolf | 2019-03-21 | 1 | -3/+6 |
| * | Improve read_verilog debug output capabilities | Clifford Wolf | 2019-03-21 | 2 | -10/+18 |
| * | fix local name resolution in prefix constructs | Zachary Snow | 2019-03-18 | 1 | -1/+5 |
| * | Improve handling of "full_case" attributes | Clifford Wolf | 2019-03-14 | 1 | -0/+9 |
| * | Improve handling of memories used in mem index expressions on LHS of an assig... | Clifford Wolf | 2019-03-12 | 1 | -5/+16 |
| * | Remove outdated "blocking assignment to memory" warning | Clifford Wolf | 2019-03-12 | 1 | -10/+0 |
| * | Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867 | Clifford Wolf | 2019-03-12 | 1 | -6/+8 |
| * | Merge pull request #858 from YosysHQ/clifford/svalabels | Clifford Wolf | 2019-03-09 | 2 | -3/+10 |
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| | * | Add support for SVA labels in read_verilog | Clifford Wolf | 2019-03-07 | 2 | -3/+10 |
| * | | Fix handling of task output ports in clocked always blocks, fixes #857 | Clifford Wolf | 2019-03-07 | 1 | -15/+18 |
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| * | Merge pull request #848 from YosysHQ/clifford/fix763 | Clifford Wolf | 2019-03-02 | 1 | -1/+5 |
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| | * | Fix error for wire decl in always block, fixes #763 | Clifford Wolf | 2019-03-02 | 1 | -1/+5 |
| * | | Only run derive on blackbox modules when ports have dynamic size | Clifford Wolf | 2019-03-02 | 2 | -0/+20 |
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| * | Fix $global_clock handling vs autowire | Clifford Wolf | 2019-03-02 | 1 | -1/+1 |
| * | Fix $readmem[hb] for mem2reg memories, fixes #785 | Clifford Wolf | 2019-03-02 | 1 | -0/+35 |
| * | Use mem2reg on memories that only have constant-index write ports | Clifford Wolf | 2019-03-01 | 2 | -0/+13 |
