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* Index struct/union members within corresponding wire chunksDag Lem2023-03-051-11/+33
| | | | | This guards against access to bits outside of struct/union members via dynamic indexing.
* Support for data and array queries on struct/union item expressionsDag Lem2023-02-151-12/+49
| | | | For now, $bits, $left, $right, $low, $high, and $size are supported.
* Merge pull request #3661 from daglem/struct-array-range-offsetJannis Harder2023-02-151-22/+31
|\ | | | | Handle range offsets in packed arrays within packed structs
| * Handle range offsets in packed arrays within packed structsDag Lem2023-02-051-22/+31
| | | | | | | | | | | | | | This brings the metadata for packed arrays in packed structs in line with the metadata for unpacked arrays, and correctly handles the case when both lsb and msb in an address range are non-zero.
* | Resolve package types in interfaces (#3658)Dag Lem2023-02-121-3/+3
|/ | | | * Resolve package types in interfaces * Added test for resolving of package types in interfaces
* Handle struct members of union type (#3641)Dag Lem2023-01-291-1/+1
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* Fixes for some of clang scan-build detected issuesMiodrag Milanovic2023-01-171-2/+1
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* Merge pull request #3467 from jix/fix_cellarray_simplifyJannis Harder2022-12-191-0/+2
|\ | | | | simplify: Do not recursively simplify AST_CELL within AST_CELLARRAY
| * simplify: Do not recursively simplify AST_CELL within AST_CELLARRAYJannis Harder2022-12-071-0/+2
| | | | | | | | | | | | Otherwise the AST_CELL simplification uses the wrong celltype before the AST_CELLARRAY simplification has a chance to unroll it and change it to the $array celltype.
* | Made make_struct_member_range side-effect-free againDag Lem2022-12-041-20/+20
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* | Support for packed multidimensional arrays within packed structsDag Lem2022-12-031-98/+78
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* Merge pull request #3551 from daglem/struct-array-swapped-rangeJannis Harder2022-12-011-20/+60
|\ | | | | Support for arrays with swapped ranges within structs
| * Added asserts for current limitation of array dimensions in packed structsDag Lem2022-11-301-0/+8
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| * Check for all cases of currently unsupported array dimensions in packed structsDag Lem2022-11-301-10/+13
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| * Support for swapped ranges in second array dimensionDag Lem2022-11-231-3/+10
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| * Support for arrays with swapped ranges within structsDag Lem2022-11-121-9/+31
| | | | | | | | | | | | This also corrects the implementation of C type arrays within structs. Fixes #3550
* | verilog: Support module-scoped task/function callsZachary Snow2022-10-291-0/+4
|/ | | | | | | | This is primarily intended to enable the standard-permitted use of module-scoped identifiers to refer to tasks and non-constant functions. As a side-effect, this also adds support for the non-standard use of module-scoped identifiers referring to constant functions, a feature that is supported in some other tools, including Iverilog.
* Encode filename unprintable charsMiodrag Milanovic2022-08-081-18/+18
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* verilog: fix size and signedness of array querying functionsJannis Harder2022-05-301-1/+1
| | | | | | | | | | genrtlil.cc and simplify.cc had inconsistent and slightly broken handling of signedness for array querying functions. These functions are defined to return a signed result. Simplify always produced an unsigned and genrtlil always a signed 32-bit result ignoring the context. Includes tests for the the relvant edge cases for context dependent conversions.
* verilog: fix $past's signednessJannis Harder2022-05-251-0/+1
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* verilog: fix signedness when removing unreachable casesJannis Harder2022-05-241-0/+1
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* sv: fix always_comb auto nosync for nested and function blocksZachary Snow2022-04-051-1/+11
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* Fix access to whole sub-structs (#3086)Kamil Rakoczy2022-02-141-5/+17
| | | | | | * Add support for accessing whole struct * Update tests Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* verilog: fix dynamic dynamic range asgn elabZachary Snow2022-02-111-17/+34
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* verilog: fix const func eval with upto variablesZachary Snow2022-02-111-3/+10
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* sv: auto add nosync to certain always_comb local varsZachary Snow2022-01-071-0/+127
| | | | | If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated.
* fix width detection of array querying function in case and case item expressionsZachary Snow2021-12-171-2/+0
| | | | | I also removed the unnecessary shadowing of `width_hint` and `sign_hint` in the corresponding case in `simplify()`.
* Support parameters using struct as a wiretype (#3050)Kamil Rakoczy2021-11-161-7/+23
| | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-251-13/+213
| | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
* verilog: fix multiple AST_PREFIX scope resolution issuesZachary Snow2021-09-211-4/+9
| | | | | | | | - Root AST_PREFIX nodes are now subject to genblk expansion to allow them to refer to a locally-visible generate block - Part selects on AST_PREFIX member leafs can now refer to generate block items (previously would not resolve and raise an error) - Add source location information to AST_PREFIX nodes
* verilog: Emit $meminit_v2 cell.Marcelina Kościelnicka2021-07-281-46/+73
| | | | Fixes #2447.
* sv: fix two struct access bugsZachary Snow2021-07-151-1/+3
| | | | | - preserve signedness of struct members - fix initial width detection of struct members (e.g., in case expressions)
* sv: fix a few struct and enum memory leaksZachary Snow2021-07-061-0/+7
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* ast: delete wires and localparams after finishing const evaluationXiretza2021-06-141-0/+8
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* verilog: fix leaking ASTNodesXiretza2021-06-141-0/+5
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* Merge pull request #2817 from YosysHQ/claire/fixemailsClaire Xen2021-06-091-1/+1
|\ | | | | Fixing old e-mail addresses and deadnames
| * Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | | | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* | verilog: check for module scope identifiers during width detectionZachary Snow2021-06-081-11/+18
| | | | | | | | | | | | | | | | The recent fix for case expression width detection causes the width of the expressions to be queried before they are simplified. Because the logic supporting module scope identifiers only existed in simplify, looking them up would fail during width detection. This moves the logic to a common helper used in both simplify() and detectSignWidthWorker().
* | mem2reg: tolerate out of bounds constant accessesZachary Snow2021-06-081-5/+42
|/ | | | This brings the mem2reg behavior in line with the nomem2reg behavior.
* sv: support tasks and functions within packagesZachary Snow2021-06-011-1/+1
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* verilog: fix case expression sign and width handlingZachary Snow2021-05-251-1/+8
| | | | | | | | | - The case expression and case item expressions are extended to the maximum width among them, and are only interpreted as signed if all of them are signed - Add overall width and sign detection for AST_CASE - Add sign argument to genWidthRTLIL helper - Coverage for both const and non-const case statements
* verilog: fix buf/not primitives with multiple outputsXiretza2021-03-171-4/+15
| | | | | | | | | | | | From IEEE1364-2005, section 7.3 buf and not gates: > These two logic gates shall have one input and one or more outputs. > The last terminal in the terminal list shall connect to the input of the > logic gate, and the other terminals shall connect to the outputs of > the logic gate. yosys does not follow this and instead interprets the first argument as the output, the second as the input and ignores the rest.
* verilog: support module scope identifiers in parametric modulesZachary Snow2021-03-161-4/+8
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* sv: allow globals in one file to depend on globals in anotherZachary Snow2021-03-121-0/+1
| | | | | | This defers the simplification of globals so that globals in one file may depend on globals in other files. Adds a simplify() call downstream because globals are appended at the end.
* verilog: Use proc memory writes in the frontend.Marcelina Kościelnicka2021-03-081-11/+47
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* sv: fix some edge cases for unbased unsized literalsZachary Snow2021-03-061-1/+21
| | | | | | - Fix explicit size cast of unbased unsized literals - Fix unbased unsized literal bound directly to port - Output `is_unsized` flag in `dumpAst`
* Implement $countones, $isunknown and $onehot{,0}Michael Singer2021-02-261-0/+28
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* Implement $countbits functionMichael Singer2021-02-261-0/+59
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* Extend simplify() recursion warningZachary Snow2021-02-261-1/+1
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* frontend: Make helper functions for printing locations.Marcelina Kościelnicka2021-02-231-24/+24
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