aboutsummaryrefslogtreecommitdiffstats
path: root/frontends/ast/simplify.cc
Commit message (Collapse)AuthorAgeFilesLines
* Fix access to whole sub-structs (#3086)Kamil Rakoczy2022-02-141-5/+17
| | | | | | * Add support for accessing whole struct * Update tests Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* verilog: fix dynamic dynamic range asgn elabZachary Snow2022-02-111-17/+34
|
* verilog: fix const func eval with upto variablesZachary Snow2022-02-111-3/+10
|
* sv: auto add nosync to certain always_comb local varsZachary Snow2022-01-071-0/+127
| | | | | If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated.
* fix width detection of array querying function in case and case item expressionsZachary Snow2021-12-171-2/+0
| | | | | I also removed the unnecessary shadowing of `width_hint` and `sign_hint` in the corresponding case in `simplify()`.
* Support parameters using struct as a wiretype (#3050)Kamil Rakoczy2021-11-161-7/+23
| | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-251-13/+213
| | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
* verilog: fix multiple AST_PREFIX scope resolution issuesZachary Snow2021-09-211-4/+9
| | | | | | | | - Root AST_PREFIX nodes are now subject to genblk expansion to allow them to refer to a locally-visible generate block - Part selects on AST_PREFIX member leafs can now refer to generate block items (previously would not resolve and raise an error) - Add source location information to AST_PREFIX nodes
* verilog: Emit $meminit_v2 cell.Marcelina Kościelnicka2021-07-281-46/+73
| | | | Fixes #2447.
* sv: fix two struct access bugsZachary Snow2021-07-151-1/+3
| | | | | - preserve signedness of struct members - fix initial width detection of struct members (e.g., in case expressions)
* sv: fix a few struct and enum memory leaksZachary Snow2021-07-061-0/+7
|
* ast: delete wires and localparams after finishing const evaluationXiretza2021-06-141-0/+8
|
* verilog: fix leaking ASTNodesXiretza2021-06-141-0/+5
|
* Merge pull request #2817 from YosysHQ/claire/fixemailsClaire Xen2021-06-091-1/+1
|\ | | | | Fixing old e-mail addresses and deadnames
| * Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | | | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* | verilog: check for module scope identifiers during width detectionZachary Snow2021-06-081-11/+18
| | | | | | | | | | | | | | | | The recent fix for case expression width detection causes the width of the expressions to be queried before they are simplified. Because the logic supporting module scope identifiers only existed in simplify, looking them up would fail during width detection. This moves the logic to a common helper used in both simplify() and detectSignWidthWorker().
* | mem2reg: tolerate out of bounds constant accessesZachary Snow2021-06-081-5/+42
|/ | | | This brings the mem2reg behavior in line with the nomem2reg behavior.
* sv: support tasks and functions within packagesZachary Snow2021-06-011-1/+1
|
* verilog: fix case expression sign and width handlingZachary Snow2021-05-251-1/+8
| | | | | | | | | - The case expression and case item expressions are extended to the maximum width among them, and are only interpreted as signed if all of them are signed - Add overall width and sign detection for AST_CASE - Add sign argument to genWidthRTLIL helper - Coverage for both const and non-const case statements
* verilog: fix buf/not primitives with multiple outputsXiretza2021-03-171-4/+15
| | | | | | | | | | | | From IEEE1364-2005, section 7.3 buf and not gates: > These two logic gates shall have one input and one or more outputs. > The last terminal in the terminal list shall connect to the input of the > logic gate, and the other terminals shall connect to the outputs of > the logic gate. yosys does not follow this and instead interprets the first argument as the output, the second as the input and ignores the rest.
* verilog: support module scope identifiers in parametric modulesZachary Snow2021-03-161-4/+8
|
* sv: allow globals in one file to depend on globals in anotherZachary Snow2021-03-121-0/+1
| | | | | | This defers the simplification of globals so that globals in one file may depend on globals in other files. Adds a simplify() call downstream because globals are appended at the end.
* verilog: Use proc memory writes in the frontend.Marcelina Kościelnicka2021-03-081-11/+47
|
* sv: fix some edge cases for unbased unsized literalsZachary Snow2021-03-061-1/+21
| | | | | | - Fix explicit size cast of unbased unsized literals - Fix unbased unsized literal bound directly to port - Output `is_unsized` flag in `dumpAst`
* Implement $countones, $isunknown and $onehot{,0}Michael Singer2021-02-261-0/+28
|
* Implement $countbits functionMichael Singer2021-02-261-0/+59
|
* Extend simplify() recursion warningZachary Snow2021-02-261-1/+1
|
* frontend: Make helper functions for printing locations.Marcelina Kościelnicka2021-02-231-24/+24
|
* Merge pull request #2594 from zachjs/func-arg-widthwhitequark2021-02-231-9/+23
|\ | | | | verilog: fix sizing of constant args for tasks/functions
| * verilog: fix sizing of constant args for tasks/functionsZachary Snow2021-02-211-9/+23
| | | | | | | | | | | | | | | | | | | | | | | | - Simplify synthetic localparams for normal calls to update their width - This step was inadvertently removed alongside `added_mod_children` - Support redeclaration of constant function arguments - `eval_const_function` never correctly handled this, but the issue was not exposed in the existing tests until the recent change to always attempt constant function evaluation when all-const args are used - Check asserts in const_arg_loop and const_func tests - Add coverage for width mismatch error cases
* | verilog: support recursive functions using ternary expressionsZachary Snow2021-02-121-19/+81
|/ | | | | | | This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls.
* verilog: refactored constant function evaluationZachary Snow2021-02-041-68/+79
| | | | | | | | | | | Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
* verilog: significant block scoping improvementsZachary Snow2021-01-311-129/+139
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
* Fix input/output attributes when resolving typedef of wireKamil Rakoczy2021-01-181-0/+3
| | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* verilog: improved support for recursive functionsZachary Snow2020-12-311-8/+26
|
* Fix elaboration of whole memory words used as indicesZachary Snow2020-12-261-1/+8
|
* Fix constants bound to redeclared function argsZachary Snow2020-12-261-5/+16
| | | | | | | | The changes in #2476 ensured that function inputs like `input x;` retained their single-bit size when instantiated with a constant argument and turned into a localparam. That change did not handle the possibility for an input to be redeclared later on with an explicit width, such as `integer x;`.
* Merge pull request #2476 from zachjs/const-arg-widthwhitequark2020-12-231-0/+8
|\ | | | | Fix constants bound to single bit arguments (fixes #2383)
| * Fix constants bound to single bit arguments (fixes #2383)Zachary Snow2020-12-221-0/+8
| |
* | Allow constant function calls in constant function argumentsZachary Snow2020-12-071-0/+5
|/
* Merge pull request #2378 from udif/pr_dollar_high_lowclairexen2020-10-011-31/+91
|\ | | | | Added $high(), $low(), $left(), $right()
| * We can now handle array slices (e.g. $size(x[1]) etc. )Udi Finkelstein2020-09-171-7/+6
| |
| * Fixed comments, removed debug messageUdi Finkelstein2020-09-161-5/+5
| |
| * Added $high(), $low(), $left(), $right()Udi Finkelstein2020-09-151-30/+91
| |
* | Merge pull request #2330 from antmicro/arrays-fix-multirange-accessclairexen2020-09-171-1/+1
|\ \ | |/ |/| Fix unsupported subarray access detection
| * Fix subarray access conditionLukasz Dalek2020-08-031-1/+1
| | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
* | Merge pull request #2352 from zachjs/const-func-localparamclairexen2020-09-011-0/+12
|\ \ | | | | | | Allow localparams in constant functions
| * | Allow localparams in constant functionsZachary Snow2020-08-201-0/+12
| | |
* | | Merge pull request #2366 from zachjs/library-formatclairexen2020-09-011-0/+11
|\ \ \ | | | | | | | | Simple support for %l format specifier
| * | | Simple support for %l format specifierZachary Snow2020-08-291-0/+11
| |/ / | | | | | | | | | | | | Yosys doesn't support libraries, so this provides the same behavior as %m, as some other tools have opted to do.
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-26 19:27:57 +0000