iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	This PR should be the base for discussion, do not merge it yet!	Udi Finkelstein	2018-03-11	1	-0/+10
\| \| \| \| \| \| \| \| \| \| \| \|	It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
*	Add $allconst and $allseq cell types	Clifford Wolf	2018-02-23	1	-1/+1
\| \| \| \|	Signed-off-by: Clifford Wolf <clifford@clifford.at>
*	Add support for "yosys -E"	Clifford Wolf	2018-01-07	1	-0/+1
\| \| \| \|	Signed-off-by: Clifford Wolf <clifford@clifford.at>
*	Fix error handling for nested always/initial	Clifford Wolf	2017-12-02	1	-0/+3
\|
*	Remove some dead code	Clifford Wolf	2017-10-10	1	-15/+0
\|
*	Allow $past, $stable, $rose, $fell in $global_clock blocks	Clifford Wolf	2017-10-10	1	-1/+5
\|
*	Allow $size and $bits in verilog mode, actually check test case	Clifford Wolf	2017-09-29	1	-1/+1
\|
*	$size() now works correctly for all cases!	Udi Finkelstein	2017-09-26	1	-17/+17
\| \| \| \|	It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
*	$size() seems to work now with or without the optional parameter.	Udi Finkelstein	2017-09-26	1	-10/+40
\| \| \| \|	Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
*	enable $bits() and $size() functions only when the SystemVerilog flag is ↵	Udi Finkelstein	2017-09-26	1	-1/+1
\| \| \| \|	enabled for read_verilog
*	Added $bits() for memories as well.	Udi Finkelstein	2017-09-26	1	-2/+26
\|
*	$size() now works with memories as well!	Udi Finkelstein	2017-09-26	1	-1/+3
\|
*	Add $size() function. At the moment it works only on expressions, not on ↵	Udi Finkelstein	2017-09-26	1	-0/+14
\| \| \| \|	memories.
*	Add $live and $fair cell types, add support for s_eventually keyword	Clifford Wolf	2017-02-25	1	-2/+2
\|
*	Fix incorrect "incompatible re-declaration of wire" error in tasks/functions	Clifford Wolf	2017-02-14	1	-2/+9
\|
*	Add $cover cell type and SVA cover() support	Clifford Wolf	2017-02-04	1	-2/+2
\|
*	Fix bug in AstNode::mem2reg_as_needed_pass2()	Clifford Wolf	2017-01-15	1	-0/+2
\|
*	Fixed handling of local memories in functions	Clifford Wolf	2017-01-05	1	-2/+2
\|
*	Added handling of local memories and error for local decls in unnamed blocks	Clifford Wolf	2017-01-04	1	-1/+10
\|
*	Added Verilog $rtoi and $itor support	Clifford Wolf	2017-01-03	1	-24/+30
\|
*	Added support for hierarchical defparams	Clifford Wolf	2016-11-15	1	-11/+32
\|
*	Fixed anonymous genblock object names	Clifford Wolf	2016-11-04	1	-1/+1
\|
*	Some fixes in handling of signed arrays	Clifford Wolf	2016-11-01	1	-0/+6
\|
*	Added $anyseq cell type	Clifford Wolf	2016-10-14	1	-2/+2
\|
*	Added $past, $stable, $rose, $fell SVA functions	Clifford Wolf	2016-09-19	1	-2/+131
\|
*	Avoid creation of bogus initial blocks for assert/assume in always @*	Clifford Wolf	2016-09-06	1	-1/+11
\|
*	Removed $aconst cell type	Clifford Wolf	2016-08-30	1	-2/+2
\|
*	Removed $predict again	Clifford Wolf	2016-08-28	1	-2/+2
\|
*	Fixed bug with memories that do not have a down-to-zero data width	Clifford Wolf	2016-08-22	1	-2/+13
\|
*	Another bugfix in mem2reg code	Clifford Wolf	2016-08-21	1	-6/+28
\|
*	Fixed finish_addr handling in $readmemh/$readmemb	Clifford Wolf	2016-08-20	1	-3/+3
\|
*	Optimize memory address port width in wreduce and memory_collect, not ↵	Clifford Wolf	2016-08-19	1	-0/+5
\| \| \| \|	verilog front-end
*	Added $anyconst and $aconst	Clifford Wolf	2016-07-27	1	-0/+4
\|
*	Using $initstate in "initial assume" and "initial assert"	Clifford Wolf	2016-07-21	1	-1/+6
\|
*	Added $initstate cell type and vlog function	Clifford Wolf	2016-07-21	1	-0/+24
\|
*	After reading the SV spec, using non-standard predict() instead of expect()	Clifford Wolf	2016-07-21	1	-2/+2
\|
*	Added basic support for $expect cells	Clifford Wolf	2016-07-13	1	-5/+7
\|
*	Fixed mem assignment in left-hand-side concatenation	Clifford Wolf	2016-07-08	1	-0/+44
\|
*	Fixed access-after-delete bug in mem2reg code	Clifford Wolf	2016-05-27	1	-6/+22
\|
*	Fixed handling of parameters and const functions in casex/casez pattern	Clifford Wolf	2016-04-21	1	-3/+15
\|
*	Do not set "nosync" on task outputs, fixes #134	Clifford Wolf	2016-03-24	1	-1/+2
\|
*	Added support for $stop system task	Clifford Wolf	2016-03-21	1	-5/+5
\|
*	Added $display %m support, fixed mem leak in $display, fixes #128	Clifford Wolf	2016-03-19	1	-20/+44
\|
*	Fixed localparam signdness, fixes #127	Clifford Wolf	2016-03-18	1	-1/+1
\|
*	Set "nosync" attribute on internal task/function wires	Clifford Wolf	2016-03-18	1	-0/+1
\|
*	Fixed some visual studio warnings	Clifford Wolf	2016-02-13	1	-2/+2
\|
*	Fixed handling of re-declarations of wires in tasks and functions	Clifford Wolf	2015-11-23	1	-7/+26
\|
*	More bugfixes in handling of parameters in tasks and functions	Clifford Wolf	2015-11-12	1	-1/+11
\|
*	Fixed handling of parameters and localparams in functions	Clifford Wolf	2015-11-11	1	-3/+3
\|
*	Import more std:: stuff into Yosys namespace	Clifford Wolf	2015-10-25	1	-12/+12
\|