| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fixed the -vout flag to -vqm in examples/intel directory | dh73 | 2017-11-14 | 4 | -4/+4 |
| * | Replace CRLF line endings with LF in de2i.qsf (quartus example) | Clifford Wolf | 2017-04-12 | 1 | -1098/+1098 |
| * | Squelch trailing whitespace | Larry Doolittle | 2017-04-12 | 4 | -28/+28 |
| * | Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs | dh73 | 2017-04-05 | 17 | -0/+1287 |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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