iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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\| *	Merge pull request #1393 from whitequark/write_verilog-avoid-init	Clifford Wolf	2019-10-27	1	-4/+5
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\| \| *	write_verilog: do not print (init) attributes on regs.	whitequark	2019-09-22	1	-4/+5
\| * \|	Bugfix in smtio vcd handling of $-identifiers	Clifford Wolf	2019-10-23	1	-6/+9
* \| \|	Rename $currQ to $abc9_currQ	Eddie Hung	2019-10-07	1	-8/+8
* \| \|	Get rid of latch_* in write_xaiger	Eddie Hung	2019-10-07	1	-7/+1
* \| \|	Remove "write_xaiger -zinit"	Eddie Hung	2019-10-07	1	-16/+6
* \| \|	Add comment on default flop init	Eddie Hung	2019-10-07	1	-0/+1
* \| \|	Get rid of output_port lookup	Eddie Hung	2019-10-07	1	-14/+8
* \| \|	Do not require changes to cells_sim.v; try and work out comb model	Eddie Hung	2019-10-05	1	-48/+70
* \| \|	Error if $currQ not found	Eddie Hung	2019-10-05	1	-0/+4
* \| \|	Fix merge issues	Eddie Hung	2019-10-04	1	-1/+1
* \| \|	Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff	Eddie Hung	2019-10-04	1	-11/+11
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\| * \|	Rename abc_* names/attributes to more precisely be abc9_*	Eddie Hung	2019-10-04	1	-9/+9
* \| \|	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-10-03	2	-20/+23
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\| * \|	Change smtbmc "Warmup failed" status to "PREUNSAT"	Clifford Wolf	2019-10-03	1	-14/+14
\| * \|	Fix btor back-end to use "state" instead of "input" for undef init bits	Clifford Wolf	2019-10-02	1	-6/+9
* \| \|	No need to punch ports at all	Eddie Hung	2019-09-30	1	-0/+24
* \| \|	Remove need for $currQ port connection	Eddie Hung	2019-09-30	1	-3/+3
* \| \|	Cleanup	Eddie Hung	2019-09-30	1	-100/+3
* \| \|	Use a cell_cache to instantiate once rather than opt_merge call	Eddie Hung	2019-09-30	1	-15/+15
* \| \|	scc call on active module module only, plus cleanup	Eddie Hung	2019-09-30	1	-8/+12
* \| \|	Use derived module	Eddie Hung	2019-09-30	1	-22/+5
* \| \|	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-09-29	1	-8/+8
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\| * \|	Merge pull request #1359 from YosysHQ/xc7dsp	Eddie Hung	2019-09-29	1	-8/+8
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\| \| * \|	"abc_padding" attr for blackbox outputs that were padded, remove them later	Eddie Hung	2019-09-23	1	-1/+6
\| \| * \|	Force $inout.out ports to begin with '$' to indicate internal	Eddie Hung	2019-09-23	1	-1/+1
\| \| * \|	When two boxes connect to each other, need not be a (* keep *)	Eddie Hung	2019-09-19	1	-6/+1
* \| \| \|	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-09-29	4	-5/+8
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\| * \| \|	Merge pull request #1413 from YosysHQ/mmicko/backend_binary_out	Miodrag Milanović	2019-09-29	3	-4/+4
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\| \| * \| \|	Add aiger and protobuf backends binary support	Miodrag Milanovic	2019-09-28	2	-3/+3
\| \| * \| \|	Support binary files for backends, fixes #1407	Miodrag Milanovic	2019-09-28	1	-1/+1
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\| * / /	Corrects btor2 backend	Aman Goel	2019-09-27	1	-1/+4
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* \| \|	Big rework; flop info now mostly in cells_sim.v	Eddie Hung	2019-09-28	1	-62/+93
* \| \|	Use abc_mergeability attr for "r" extension	Eddie Hung	2019-09-27	1	-58/+66
* \| \|	Fix infinite recursion	Eddie Hung	2019-09-27	1	-1/+1
* \| \|	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-09-27	4	-10/+29
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\| * \|	Add "write_aiger -L"	Clifford Wolf	2019-09-18	1	-5/+16
\| * \|	Fix stupid bug in btor back-end	Clifford Wolf	2019-09-18	1	-1/+1
\| * \|	backends: smt2: use $(CXX) variable for compiler	Sean Cross	2019-09-08	1	-1/+1
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\| *	Recognise built-in types (e.g. $_DFF_*)	Eddie Hung	2019-08-30	1	-3/+3
\| *	Revert "Revert "Fix omode which inserts an output if none exists (otherwise a...	Eddie Hung	2019-08-28	1	-7/+8
\| *	Revert "Output "h" extension only if boxes"	Eddie Hung	2019-08-28	1	-32/+28
\| *	Output "h" extension only if boxes	Eddie Hung	2019-08-21	1	-28/+32
\| *	Revert "Fix omode which inserts an output if none exists (otherwise abc9 brea...	Eddie Hung	2019-08-21	1	-8/+7
\| *	Fix omode which inserts an output if none exists (otherwise abc9 breaks)	Eddie Hung	2019-08-20	1	-7/+8
\| *	Revert "Only xaig if GetSize(output_bits) > 0"	Eddie Hung	2019-08-20	1	-149/+147
\| *	Only xaig if GetSize(output_bits) > 0	Eddie Hung	2019-08-20	1	-147/+149
* \|	Revert "Remove sequential extension"	Eddie Hung	2019-08-20	1	-29/+270
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*	Remove sequential extension	Eddie Hung	2019-08-20	1	-270/+29
*	Do not sigmap!	Eddie Hung	2019-08-20	1	-2/+2