Commit message (Collapse) | Author | Age | Files | Lines | ||||||
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* | | | | Cleanup; reduce Module::derive() calls | Eddie Hung | 2020-05-14 | 1 | -18/+20 | |||||
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* | | | | xaiger: no longer use nonstandard even/odd to designate +ve/-ve polarity | Eddie Hung | 2020-05-14 | 1 | -16/+5 | |||||
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* | | | | abc9: not enough to techmap_fail on (* init=1 *), hide them using $__ | Eddie Hung | 2020-05-14 | 1 | -0/+1 | |||||
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* | | | | Revert "Merge pull request #1917 from YosysHQ/eddie/abc9_delay_check" | Eddie Hung | 2020-05-14 | 1 | -4/+0 | |||||
| | | | | | | | | | | | | | | | | | | | | This reverts commit 759283fa65b1195ebe3a5bc6890ec622febca0eb, reversing changes made to f41c7ccfff4bf104c646ca4b85e079a0f91c9151. | |||||||||
* | | | | xaiger: always sort input/output bits by port id | Eddie Hung | 2020-05-14 | 1 | -12/+10 | |||||
| | | | | | | | | | | | | | | | | redundant for normal design, but necessary for holes | |||||||||
* | | | | abc9: generate $abc9_holes design instead of <name>$holes | Eddie Hung | 2020-05-14 | 1 | -3/+9 | |||||
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* | | | | aiger/xaiger: use odd for negedge clk, even for posedge | Eddie Hung | 2020-05-14 | 1 | -6/+10 | |||||
| | | | | | | | | | | | | | | | | Since abc9 doesn't like negative mergeability values | |||||||||
* | | | | xaiger: update help text | Eddie Hung | 2020-05-14 | 1 | -4/+4 | |||||
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* | | | | xaiger: do not treat (* init=1'bx *) as 1'b0 | Eddie Hung | 2020-05-14 | 1 | -1/+1 | |||||
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* | | | | xaiger: when -dff use (* init *) for initial state | Eddie Hung | 2020-05-14 | 1 | pre { line-height: 125%; margin: 0; }
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.highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */#!/usr/bin/env python3
import visa
import time
import sys
def test_idn():
idn = inst.query("*idn?");
assert (idn == "TinyUSB,ModelNumber,SerialNumber,FirmwareVer123456\r\n")
assert (inst.is_4882_compliant)
def test_echo(m,n):
longstr = "0123456789abcdefghijklmnopqrstuvwxyz" * 50
t0 = time.monotonic()
#Next try echo from 1 to 175 characters (200 is max buffer size on DUT)
for i in range(m,n):
#print(i)
x = longstr[0:i]
xt = x + inst.write_termination
y = inst.query(x)
#print(x)
#print (":".join("{:02x}".format(ord(c)) for c in xt))
#print (":".join("{:02x}".format(ord(c)) for c in y))
assert(xt == y), f"failed i={i}"
#inst.read_stb();# Just to make USB logging easier by sending a control query (bad thing is that this made things slow)
t = time.monotonic() - t0
print(f" elapsed: {t:0.3} sec")
def test_trig():
# clear SRQ
inst.read_stb()
assert (inst.read_stb() == 0)
inst.assert_trigger()
time.sleep(0.3) # SRQ may have some delay
assert (inst.read_stb() & 0x40), "SRQ not set after 0.3 seconds"
assert (inst.read_stb() == 0)
def test_mav():
inst.write("delay 50")
inst.read_stb() # clear STB
assert (inst.read_stb() == 0)
inst.write("123")
time.sleep(0.3)
assert (inst.read_stb() & 0x10), "MAV not set after 0.5 seconds"
rsp = inst.read()
assert(rsp == "123\r\n")
def test_srq():
assert (inst.read_stb() == 0)
inst.write("123")
#inst.enable_event(visa.constants.VI_EVENT_SERVICE_REQ, visa.constants.VI_QUEUE)
#waitrsp = inst.wait_on_event(visa.constants.VI_EVENT_SERVICE_REQ, 5000)
#inst.discard_events(visa.constants.VI_EVENT_SERVICE_REQ, visa.constants.VI_QUEUE)
#inst.wait_for_srq()
time.sleep(0.3)
stb = inst.read_stb()
msg = "SRQ not set after 0.5 seconds, was {:02x}".format(stb)
assert (stb == 0x50),msg
assert (inst.read_stb() == 0x10), "SRQ set at second read!"
rsp = inst.read()
assert(rsp == "123\r\n")
def test_read_timeout():
inst.timeout = 500
# First read with no MAV
inst.read_stb()
assert (inst.read_stb() == 0)
inst.write("delay 500")
t0 = time.monotonic()
try:
rsp = inst.read()
assert(false), "Read should have resulted in timeout"
except visa.VisaIOError:
print(" Got expected exception")
t = time.monotonic() - t0
assert ((t*1000.0) > (inst.timeout - 300))
assert ((t*1000.0) < (inst.timeout + 300))
print(f"Delay was {t:0.3}")
# Response is still in queue, so send a clear (to be more helpful to the next test)
inst.clear()
time.sleep(0.3)
assert(0 == (inst.read_stb() & 0x10)), "MAV not reset after clear"
def test_abort_in():
inst.timeout = 200
# First read with no MAV
inst.read_stb()
assert (inst.read_stb() == 0)
inst.write("delay 500")
inst.write("xxx")
t0 = time.monotonic()
try:
rsp = inst.read()
assert(false), "Read should have resulted in timeout"
except visa.VisaIOError:
print(" Got expected exception")
t = time.monotonic() - t0
assert ((t*1000.0) > (inst.timeout - 300))
assert ((t*1000.0) < (inst.timeout + 300))
print(f" Delay was {t:0.3}")
# Response is still in queue, so send a clear (to be more helpful to the next test)
inst.timeout = 800
y = inst.read()
assert(y == "xxx\r\n")
def test_indicate():
# perform indicator pulse
usb_iface = inst.get_visa_attribute(visa.constants.VI_ATTR_USB_INTFC_NUM)
retv = inst.control_in(request_type_bitmap_field=0xA1, request_id=64, request_value=0x0000, index=usb_iface, length=0x0001)
assert((retv[1] == visa.constants.StatusCode(0)) and (retv[0] == b'\x01')), f"indicator pulse failed: retv={retv}"
def test_multi_read():
old_chunk_size = inst.chunk_size
longstr = "0123456789abcdefghijklmnopqrstuvwxyz" * 10
timeout = 10
x = longstr[0:174]
inst.chunk_size = 50 # Seems chunk size only applies to read but not write
inst.write(x)
# I'm not sure how to request just the remaining bit using a max count... so just read it all.
y = inst.read()
assert (x + "\r\n" == y)
#inst.chunk_size = old_chunk_size
def test_stall_ep0():
usb_iface = inst.get_visa_attribute(visa.constants.VI_ATTR_USB_INTFC_NUM)
inst.read_stb()
# This is an invalid request, should create stall.
try:
retv = inst.control_in(request_type_bitmap_field=0xA1, request_id=60, request_value=0x0000, index=usb_iface, length=0x0001)
assert false
except visa.VisaIOError:
pass
assert (inst.read_stb() == 0)
rm = visa.ResourceManager()
reslist = rm.list_resources("USB?::?*::INSTR")
print(reslist)
if (len(reslist) == 0):
sys.exit()
inst = rm.open_resource(reslist[0]);
inst.timeout = 3000
inst.clear()
print("+ IDN")
test_idn()
print("+test abort in")
test_abort_in()
inst.timeout = 2000
print("+ multi read")
test_multi_read()
print("+ echo delay=0")
inst.write("delay 0")
test_echo(1,175)
print("+ echo delay=2")
inst.write("delay 2")
test_echo(1,175)
print("+ echo delay=150")
inst.write("delay 150")
test_echo(53,76)
test_echo(165,170)
print("+ Read timeout (no MAV)")
test_read_timeout()
print("+ Test EP0 stall recovery")
test_stall_ep0()
print("+ MAV")
test_mav()
print("+ SRQ")
test_srq()
print("+ indicate")
test_indicate()
print("+ TRIG")
test_trig()
# Untested:
# abort bulk out
# LLO, GTL, etc
# Throughput rate?
# Transmitting a message using multiple transfers
inst.close()
print("Test complete")
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Signed-off-by: Claire Wolf <claire@symbioticeda.com> | ||||
* | | Merge pull request #1961 from whitequark/paramod-original-name | whitequark | 2020-04-21 | 1 | -11/+2 | |||||
|\ \ | |/ |/| | ast, rpc: record original name of $paramod\* as \hdlname attribute | |||||||||
| * | ast, rpc: record original name of $paramod\* as \hdlname attribute. | whitequark | 2020-04-18 | 1 | -11/+2 | |||||
| | | | | | | | | | | | | | | | | | | | | The $paramod name mangling is not invertible (the \ character, which separates the module name from the parameters, is valid in the module name itself), which does not stop people from trying to invert it. This commit makes it easy to invert the name mangling by storing the original name explicitly, and fixes the firrtl backend to use the newly introduced attribute. | |||||||||
* | | cxxrtl: provide attributes to black box factories, too. | whitequark | 2020-04-19 | 2 | -49/+57 | |||||
| | | | | | | | | | | | | | | | | | | Both parameters and attributes are necessary because the parameters have to be the same between every instantiation of the cell, but attributes may well vary. For example, for an UART PHY, the type of the PHY (tty, pty, socket) would be a parameter, but configuration of the implementation specified by the type (socket address) would be an attribute. | |||||||||
* | | cxxrtl: add templated black box support. | whitequark | 2020-04-18 | 1 | -16/+193 | |||||
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* | | cxxrtl: make eval() and commit() inline in blackboxes. | whitequark | 2020-04-18 | 1 | -82/+103 | |||||
| | | | | | | | | | | This change is a preparation for template blackboxes. It has no effect on current generated code. | |||||||||
* | | cxxrtl: add simple black box support. | whitequark | 2020-04-18 | 2 | -70/+311 | |||||
| | | | | | | | | | | | | | | This commit adds support for replacing RTLIL modules with CXXRTL black boxes. Black box port widths may not depend on the parameters with which it is instantiated (yet); the parameters may only be used to change the behavior of the black box. | |||||||||
* | | cxxrtl: use ID::X instead of ID(X). NFC. | whitequark | 2020-04-18 | 1 | -107/+107 | |||||
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* | | cxxrtl: correctly handle `sync always` rules. | whitequark | 2020-04-17 | 1 | -3/+13 | |||||
|/ | | | | Fixes #1948. | |||||||||
* | Merge pull request #1947 from whitequark/cxxrtl-usability | whitequark | 2020-04-16 | 2 | -10/+19 | |||||
|\ | | | | | cxxrtl: minor documentation and usability improvements | |||||||||
| * | cxxrtl: make ROMs writable, document memory::operator[]. | whitequark | 2020-04-16 | 2 | -4/+6 | |||||
| | | | | | | | | | | | | | | | | | | | | | | There is no practical benefit from using `const memory` for ROMs; it uses an std::vector internally, which prevents contemporary compilers from constant-propagating ROM contents. (It is not clear whether they are permitted to do so.) However, there is a major benefit from using non-const `memory` for ROMs, which is the ability to dynamically fill the ROM for each individual simulation. | |||||||||
| * | cxxrtl: fix misleading example, caution about race conditions. | whitequark | 2020-04-16 | 1 | -4/+13 | |||||
| | | | | | | | | Fixes #1944. | |||||||||
| * | cxxrtl: remove inaccurate comment. NFC. | whitequark | 2020-04-16 | 1 | -2/+0 | |||||
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* | | Merge pull request #1797 from epfl-vlsc/firrtl_backend_fileinfo | Claire Wolf | 2020-04-16 | 1 | -29/+51 | |||||
|\ \ | |/ |/| | Keep file information when emitting firrtl |